RTL8201FL-VB-CG

RTL8201F-VB-CGRTL8201FL-VB-CGRTL8201FN-VB-CGSINGLE-CHIP/PORT10/100METHERNETPHYCEIVERWITHAUTOMDIXDATASHEET(CONFIDENTIAL:DevelopmentPartnersOnly)Rev.1.430November2011TrackID:JATR-2265-11RealtekSemiconductorCorp.No.2,InnovationRoadII,HsinchuSciencePark,Hsinchu300,TaiwanTel.:[phone].Fax:[phone]:JATR-2265-11Rev.1.4COPYRIGHT©2011RealtekSemiconductorCorp.Allrightsreserved.Nopartofthisdocumentmaybereproduced,transmitted,transcribed,storedinaretrievalsystem,ortranslatedintoanylanguageinanyformorbyanymeanswithoutthewrittenpermissionofRealtekSemiconductorCorp.DISCLAIMERRealtekprovidesthisdocument‘asis’,withoutwarrantyofanykind.Realtekmaymakeimprovementsand/orchangesinthisdocumentorintheproductdescribedinthisdocumentatanytime.Thisdocumentcouldincludetechnicalinaccuraciesortypographicalerrors.TRADEMARKSRealtekisatrademarkofRealtekSemiconductorCorporation.Othernamesmentionedinthisdocumentaretrademarks/registeredtrademarksoftheirrespectiveowners.LICENSEThisproductiscoveredbyoneormoreofthefollowingpatents:US5,307,459,US5,434,872,US5,732,094,US6,570,884,US6,115,776,andUS6,327,625.USINGTHISDOCUMENTThisdocumentisintendedforthesoftwareengineer’sreferenceandprovidesdetailedprogramminginformation.Thougheveryefforthasbeenmadetoensurethatthisdocumentiscurrentandaccurate,moreinformationmayhavebecomeavailablesubsequenttotheproductionofthisguide.RTL8201F/RTL8201FL/RTL8201FNDatasheetSingle-Chip/Port10/100MEthernetPHYceiverwithAutoMDIXiiiTrackID:JATR-2265-11Rev.1.4REVISIONHISTORYRevisionReleaseDateSummary1.02010/12/17Firstrelease.1.12011/02/18RevisedtoVBmodel.RevisedTable22Register30InterruptIndicatorsandSNRDisplayRegister,page21.Addedinterruptfunction.AddedMMDRegisterMappingandDefinitionsection.Revisedsection8.2Interrupt,page31.RevisedTable46AbsoluteMaximumRatings,page44.Revised9.1.3PowerOnandPHYResetSequence,page45.RevisedTable49RMIIInputModePowerDissipation(WholeSystem),page46.1.22011/04/21RevisedFigure2BlockDiagram,page4.RevisedTable3RMIIInterface,page10.RevisedTable7DeviceConfigurationInterface,page11.RevisedTable9ResetandOtherPins,page14.RevisedTable11Register0BasicModeControlRegister,page15.RevisedTable15Register4Auto-NegotiationAdvertisementRegister(ANAR),page17.RevisedTable20Register24,page20.RevisedTable24Page4Register16EEECapabilityEnableRegister,page22.RevisedTable25Page4Register21EEECapabilityRegister,page22.RevisedTable30Page7Register19,page24.Addedsection7.21Page7Register24SpreadSpectrumClockRegister,page25.Revisedsection8.1.2SerialManagementInterface,page29.Revisedsection8.7ResetandTransmitBias,page38.Addedsection8.13SpreadSpectrumClock(SSC),page43.AddedFigure21MIIInterfaceSetup/HoldTimeDefinitions,page47.AddedFigure26RMIIInterfaceSetup,HoldTime,andOutputDelayTimeDefinitions,page49.AddedFigure28MDC/MDIOInterfaceSetup,HoldTime,andValidfromMDCRisingEdgeTimeDefinitions,page51.1.32011/07/14AddedFigure1ApplicationDiagram,page3.RevisedTable30Page7Register19Interrupt,WOLEnable,andLEDsFunctionRegisters,page24.AddedTable34EEEPC1R(PCSControl1Register,MMDDevice3,Address0x00),page25.AddedTable35EEEPS1R(PCSStatus1Register,MMDDevice3,Address0x01),page26.Addedsection8.4.1LEDandPHYAddress,page32.Addedsection8.4.8EEELED,page36.Revisedsection8.7ResetandTransmitBias,page38.1.42011/11/30RevisedFigure2BlockDiagram,page4.RevisedTable4ClockInterface,page10(CKXTAL2pinrevisedfromItoIO).RTL8201F/RTL8201FL/RTL8201FNDatasheetSingle-Chip/Port10/100MEthernetPHYceiverwithAutoMDIXivTrackID:JATR-2265-11Rev.1.4TableofContents1.GENERALDESCRIPTION..............................................................................................................................................12.FEATURES.........................................................................................................................................................................23.APPLICATIONS................................................................................................................................................................33.1.APPLICATIONDIAGRAM...............................................................................................................................................34.BLOCKDIAGRAM...........................................................................................................................................................45.PINASSIGNMENTS.........................................................................................................................................................55.1.RTL8201F(32-PIN).....................................................................................................................................................55.2.GREENPACKAGEANDVERSIONIDENTIFICATION........................................................................................................55.3.RTL8201FL(48-PIN).....................................................................