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摘要近年来，以电池作为电源的电子产品得到广泛使用，迫切要求采用低电压的模拟电路来降低功耗，所以低电压、低功耗模拟电路设计技术正成为研究的热点。本文主要讨论电感负反馈cascode-CMOS-LNA（共源共栅低噪声放大器）的噪声优化技术，同时也分析了噪声和输入同时匹配的SNIM技术。以噪声参数方程为基础，列出了简单易懂的设计原理。为了实现低电压、低噪声、高线性度的设计指标，在本文中使用了三种设计技术。第一，本文以大量的篇幅推导出了一个理想化的噪声结论，并使用Matlab分析了基于功耗限制的噪声系数，取得最优化的晶体管尺寸。第二，为了实现低电压设计，引用了一个折叠式的共源共栅结构低噪声放大器。第三，通过线性度的理论分析并结合实验仿真的方法，得出了设计一个高线性度的最后方案。另外，为了改善射频集成电路的器件参数选择的灵活性，在第四章中使用了一种差分结构。所设计的电路用CHARTER公司0.25μmCMOS工艺技术实现，并使用Cadence的spectreRF工具进行仿真分析。本文使用的差分电路结构只进行了电路级的仿真，而折叠式的共源共栅电路进行了电路级的仿真、版图设计、版图参数提取、电路版图一致性检查和后模拟，完成了整个低噪声放大器的设计流程。折叠式低噪声放大器的仿真结果为：噪声系数NF为1.30dB，反射参数S11、S12、S22分别为-21.73dB、-30.62dB、-23.45dB，正向增益S21为14.27dB，1dB压缩点为-12.8dBm，三阶交调点IIP3为0.58dBm。整个电路工作在1V电源下，消耗的电流为8.19mA，总的功耗为8.19mW。所有仿真的技术指标达到设计要求。关键字：低噪声放大器；噪声系数；低电压、低功耗；共源共栅；噪声匹配ABSTRACTInrecentyears,electronicswithbatterysupplyarewidelyused,whichcriesforadoptinglowvoltageanalogcircuitstoreducepowerconsumption,solowvoltage,lowpoweranalogcircuitdesigntechniquesarebecomingresearchhotspot.ThispapermainlydiscussesnoisefigureoptimizationtechniquesforinductivelydegeneratedcascodeCMOSlow-noiseamplifiers(LNAs)withon-chipinductors.Anditreviewsandanalyzessimultaneousnoiseandinputmatchingtechniques(SNIM).Basedonthenoiseparameterequations,thispaperprovidesclearunderstandingofthedesignprinciple.Inordertoachievelow-voltage,lownoise,high-linearityofthedesignspecifications,inthispaperbythreedesigntechnology.Firstly,usingMatlabtoolanalyzesnoisefigurebasedonpower-constrained,andobtaintheoptimumtransistorsize.Secondly,designafolded-cascode-typeLNAtoreducethepowersupper.Third,throughtheoreticalanalysisofLinearandcombinesimulationmethods,Iobtainafinaldesignofahigh-linearity.Ontheotherside,inordertoimprovetheradiofrequencyintegratedcircuitdeviceparametersofflexibility,thispaperpresentsadifferenceinthestructureinthefourthchapter.Theproposedcircuitdesignisrealizedusingcsm25RF0.25μmCMOStechnology,simulatedwithCadencespecterRF.Basedoncsm25RF0.25μmCMOStechnology,theresultingdifferentialLNAachieves1.32dBnoisefigure,-20.65dBS11,-24dBS22,-30.27S12,14dBS21.TheLNA's1-dBcompressionpointis-13.3dBm,andIIP3is-0.79dBm,withthecorecircuitconsuming8.1mAfroma1Vpowersupply.Keywords：low-noiseamplifier(LNA)；noisefigure；lowvoltagelowpower；cascode；noisematching目录第一章绪论..........................................11.1课题背景.......................................................11.2研究现状及存在的问题...........................................21.3本论文主要工作.................................................31.4论文内容安排...................................................3第二章射频电路噪声理论和线性度分析........................42.1噪声理论.......................................................42.1.1噪声的表示方法.............................................42.1.2本文研究的器件噪声类型.....................................52.1.2.1热噪声.................................................52.1.2.2MOS噪声模型............................................62.1.3两端口网络噪声理论.........................................72.1.4多级及联网络噪声系数计算...................................92.2MOSFET两端口网络噪声参数的理论分析...........................102.3降低噪声系数的一般措施........................................132.4MOSLNA线性度分析............................................142.4.11dB压缩点................................................142.4.2三阶输入交调点IIP3.......................................162.4.3多级及联网络线性度表示方法（起最重要作用的线性级）........172.5小结..........................................................18第三章CMOS低噪声放大器的设计理论推导.....................203.1LNA设计指标..................................................203.1.1噪声系数..................................................203.1.2增益......................................................203.1.3线性度....................................................203.1.4输入输出匹配..............................................213.1.5输入输出隔离..............................................213.1.6电路功耗..................................................213.1.7稳定性....................................................213.2CMOSLNA拓扑结构分析.........................................213.2.1基本结构及比较............................................213.2.2源极去耦与噪声、输入同时匹配(SNIM)的设计..................223.2.3共源共栅电路结构（cascode）...............................273.2.4功率限制的单端分析—获得最佳化的宽长比....................293.3其它改进型电路比较............................................313.4偏置电路的设计................................................333.5CASCODE设计结论................................................34第四章2.4GHZLNA电路设计..............................354.1工艺库的元器件................................................354.2差分CASCODE电路...............................................354.2.1差分电路的设计............................................354.2.2差分电路的电路极仿真......................................374.3单端CASCODE电路...............................................394.3.1单端电路的设计............................................394.3.2单端电路的电路级仿真......................................434.3.3单端电路的版图设计、提取及后模拟..........................454.4电路级仿真和后模拟仿真总结....................................484.5与其它电路的比较..............................................49结束语.............................................51致谢...............