东南大学-计算结构-课程设计-POC设计报告

TheDesignReportoftheparalleloutputcontroller(POC)COA-POCSoutheastUniversityComputerOrganizationandArchitectureCourseDesignTheReportoftheparalleloutputcontroller(POC)SchoolofInformationScienceandEngineeringSoutheastUniversity2014TheDesignReportoftheparalleloutputcontroller(POC)COA-POCSoutheastUniversity1.PurposeThepurposeofthisprojectistodesignandsimulateaparalleloutputcontroller(POC)whichactsaninterfacebetweensystembusandprinter.TheAltera’sMaxplusIIEDAtoolisrecommendedandprovidedforsimulation.2.IntroductionandrequirementsBasicintroductionPOCisoneofthemostcommonI/Omodules,namelytheparalleloutputcontroller.Itplaystheroleofaninterfacebetweenthecomputersystembusandtheperipheral(suchasaprinterorotheroutputdevices).ArchitecturalModelFigure1PrinterConnectionFigure1showstheconnectingofaprintertothesystembusthroughthePOC.ThecommunicationbetweenPOCandtheprinteriscontrolledbya“handshake”protocolillustratedinFigure2.TheDesignReportoftheparalleloutputcontroller(POC)COA-POCSoutheastUniversityFigure2Thehandshake-timingdiagrambetweenPOCandtheprinterThehandshakingprocessisdescribedasfollows:Whentheprinterisreadytoreceiveacharacter,itholdsRDY=1.ThePOCmustthenholdacharacteratPD(paralleldata)portandproduceapulseattheterminalTR(transferrequest).TheprinterwillchangeRDYto0,takethecharacteratPDandholdtheRDYat0untilthecharacterhasbeenprinted(e.g.5or10ms),thensetRDY=1againwhenitisreadytoreceivethenextcharacter.(Supposetheprinterhasonlyaonecharacter“buffer”register,sothateachcharactermustbeprintedbeforethenextcharacterissent).3.DesignofTopSchematicFigure3TheTopSchematicofthesimulatedprinterandPOCTherearethreemodulesinthefigure:theCPU,thePrinterandthePOC.Accordingtothehintsinthedirection,weknowthatinordertosimulatethePOCbycomputer,asimulatedprinterisbeenwritten.TheDesignReportoftheparalleloutputcontroller(POC)COA-POCSoutheastUniversity4.DesignofEachModule4.1CPUFigure4TheSchematicSymbolofCPUModuleInput：PinFunctionCLKClockRSTReset,0ValidIRQInterruptRequestReceivedDin(7:0)DataInputFromBUSModuleOutput：PinFunctionRWRead/WriteOperationIndicatorADDR(7:0)TargetAddressIndicatorDout(7:0)DataOutputToBUS4.2POCFigure5TheSchematicSymbolofPOCTheDesignReportoftheparalleloutputcontroller(POC)COA-POCSoutheastUniversityModuleInput：PinFunctionCLKClockRSTReset,0ValidRWRead/WriteOperationIndicatorRDYPeripheralReadyIndicatorADDR(7:0)TargetAddressIndicatorDin(7:0)DataInputFromCPUModuleOutput：PinFunctionIRQInterruptRequestToCPUTRTransferRequesttoPeripheralpoc_SR(7:0)ShowInternalRegisterofPOCpoc_BR(7:0)ShowInternalRegisterofPOCPDDataSendtoPrinterDout(7:0)DataOutputToCPU4.3PrinterFigure6TheSchematicSymbolofPrinterModuleInput：PinFunctionCLKClockRSTReset,0ValidTRTransferRequestFromPOCPD(7:0)DataSendFromPOCTheDesignReportoftheparalleloutputcontroller(POC)COA-POCSoutheastUniversityModuleOutput：PinFunctionRDYPrinterIdleIndicatorprintingShowwhatthePrinterisprinting5.SimulationResults5.0IntroductionFollowingistheSimulationWaveforms.0xF0issettobePOCSRaddressand0xF1issettobePOCBRaddress.5.1QuerymodeFigure7-1:CPUSetsADDRtobe0xF0togetPOCStatus(SR).Figure7-2:POCisidle,CPUsendsnewdatatoPOCBufferRegister(BR,address0xF1).TheDesignReportoftheparalleloutputcontroller(POC)COA-POCSoutheastUniversityFigure7-3:CPUrefreshPOC-SR.Figure7-4:POCputsdataonPD,startinghandshakewithprinter.Figure7-5:TRissethigh,theprintergetsthedata,thenstartingprinting.TheDesignReportoftheparalleloutputcontroller(POC)COA-POCSoutheastUniversityFigure7-6:Printingprocessfinished,RDYturnhightoinformPOCthatprinterisidle.Figure7-7:WhenPOCandprinterisbusy,CPUquerywillbedenied,sothatCPUwillnotsendnewdatatoPOC.5.2InterruptModeFigure8-1:IRQvalid,CPUTurnintoInterruptProgram.TheDesignReportoftheparalleloutputcontroller(POC)COA-POCSoutheastUniversityFigure8-2:WithoutaccesstoPOC-SR,CPUwritesdatatoBR(0xF1)directly.Figure8-3:CPUrefreshPOC-SR(0xF0).Figure8-4:HandshakebetweenPOCandtheprinter.Theprinterstartsprinting.TheDesignReportoftheparalleloutputcontroller(POC)COA-POCSoutheastUniversityFigure8-5:Printingprocessfinished,RDYturnhightoinformPOCthatprinterisidle.Figure8-6:POCsetIRQvalidtoinformCPUthattheprinterisavailable.---Appendix:/**********CommonMacro.v*************/`definebit4[3:0]`definebit8[7:0]`definereg4reg[3:0]`definereg8reg[7:0]`definereg16reg[15:0]`definewire4wire[3:0]`definewire8wire[7:0]`definewire16wire[15:0]/**********EndofCommonMacro.v*************/TheDesignReportoftheparalleloutputcontroller(POC)COA-POCSoutheastUniversity/**********CPU.v*************/`include“CommonMacro.v”moduleCPU(inputCLK,inputRST,output`reg8ADDR,outputregRW,input`bit8Din,output`reg8Dout,inputIRQ);///---------///endmodule/**********EndofCPU.v*************//**********POC.v*************/modulePOC(inputCLK,inputRST,input`bit8ADDR,inputRW,input`bit8Din,output`bit8Dout,output`bit8poc_SR,output`bit8poc_BR,outputIRQ,inputRDY,outputregTR,output`reg8PD);///---------///endmodule/**********EndofPOC.v*************/TheDesignReportoftheparalleloutputcontroller(POC)COA-POCSoutheastUniversity/**********printer.v*************/moduleprinter(inputCLK,i