DLX指令集

DLX指令集,BYU版本注意8条指令已经加入到此版本的指令集中。这些指令既没有出现在Hennessy和Patterson的课本中，也没有列在Sailer和Kaeli合编的TheDLXInstructionSetArchitectureHandbook一书中。新的指令是：sgeu,sgtu,sleu,sltu--allcomparesusingunsignedvalues--alongwithanimmediateformofeach.ThenewinstructionswereaddedtosimplifytheDLXbackendforlcc.标记符号意义x_ybityofxx_y..zbitsytozofx(rightjustified)x^yxx....x(xrepeatedytimes)x##yxy(xconcatenatedwithy)IR指令寄存器IAR中断地址寄存器PC程序计数器R[rega]整数寄存器[IR_6..10]R[regb]整数寄存器[IR_11..15]R[regc]整数寄存器[IR_16..20]F[frega]浮点寄存器[IR_6..10]F[fregb]浮点寄存器[IR_11..15]F[fregc]浮点寄存器[IR_16..20]D[drega]doubleregister[IR_6..10]D[dregb]doubleregister[IR_11..15]D[dregc]doubleregister[IR_16..20]imm16valueof(IR_16)^16##IR_16..31uimm16valueof0^16##IR_16..31imm26valueof(IR_6)^6##IR_6..0fpsfloatingpointstatusbit--a32-bittransfer--nann-bittransfer符号意义赋值操作x_yx的第y位x_y..zx的第y到z位xy..zx的第y到z位x^y对x复制y次。例如：0^16表示一个16位长的全0字段x##y用于两个字段的拼接，并且可以出现在数据传送的任何一边IR指令寄存器IAR中断地址寄存器PC程序计数器Mem存储器Regs寄存器组[]表示内容Mem[]存储器的内容Mem[Regs[R1]]以寄存器R1中的内容作为地址的存储器单元中的内容R[rega]整数寄存器[IR_6..10]R[regb]整数寄存器[IR_11..15]R[regc]整数寄存器[IR_16..20]F[frega]浮点寄存器[IR_6..10]F[fregb]浮点寄存器[IR_11..15]F[fregc]浮点寄存器[IR_16..20]D[drega]doubleregister[IR_6..10]D[dregb]doubleregister[IR_11..15]D[dregc]doubleregister[IR_16..20]imm16表示(IR_16)^16##IR_16..31uimm16表示0^16##IR_16..31注意/假设Bitsarenumberedfrom0(themostsignificantbit)to31(theleastsignificantbit).Alltransfersare32bitsunlessotherwisespecified,withtheexceptionofdoubleprecisionfpoperationswhichare64bittransfersunlessotherwisenoted.Allintegeroperationsareon32-bitintegers.Allassignmentstointegerregister[x]areconditionalonxnotbeingzero.Register0hasahardwired{\emzero}valueandcannotbemodified.Doubleregister[x]isa64bitquantitythatrepresentsthesamestorageasfpregister[x]andfpregister[x+1].Onlyevenvaluesofxareallowed(doubleregisteraddressesarealigned).Singleprecisionfloatingpointis32bitsanddoubleprecisionfloatingpointis64bits.Theexactfloatingpointformatusedisthatofthemachineonwhichthesimulatorisrunning.ThespecificationsforbranchesandjumpsassumethatthePChasnotyetbeenincremented(forthenextinstruction)whenthespecifiedactionsareperformed.Notethatthisdoesnotrepresenttheactualbehaviorinanyreasonablepipelinedimplementation;itisassumedmerelytosimplifythedescription.Memorywillbestoredinbigendianformatandalleffectiveaddressesmustbealignedwiththedatatype.InstructionsaddEx:addr1,r2,r3R[regc]--R[rega]+R[regb]Allaresignedintegers.adddEx:adddf4,f4,f6D[dregc]--D[drega]+D[dregb]Allaredoubleprecisionfloatingpointnumbers.addfEx:addff3,f4,f5F[fregc]--F[frega]+F[fregb]Allaresingleprecisionfloatingpointnumbers.addiEx:addir5,r2,#5R[regb]--R[rega]+imm16Allaresignedintegers.adduEx:addur2,r3,r4R[regc]--R[rega]+R[regb]Allareunsignedintegers.adduiEx:adduir2,r3,#28R[regb]--R[rega]+uimm16Allareunsignedintegers.andEx:andr2,r3,r4R[regc]--R[rega]&R[regb]Allareunsignedintegers.Logical`and'isperformedonabitwisebasis.andiEx:andir3,r4,#5R[regb]--R[rega]&uimm16Allareunsignedintegers.Logical`and'isperformedonabitwisebasis.beqzEx:beqzr1,labelif(R[rega]==0)PC--PC+imm16+4bfpfEx:bfpflabelif(fps==0)PC--PC+imm16+4fpsisthefloatingpointstatusbit.bfptEx:bfptlabelif(fps==1)PC--PC+imm16+4fpsisthefloatingpointstatusbit.bnezEx:bnezr1,labelif(R[rega]!=0)PC--PC+imm16+4cvtd2fEx:cvtd2ff1,f4F[fregc]--(float)D[drega]Convertsdoubleprecisionfloatingpointvaluetosingleprecisionfloatingpointvalue.cvtd2iEx:cvtd2if1,f0F[fregc]--(int)D[drega]Convertsdoubleprecisionfloatingpointvaluetointeger.cvtf2dEx:cvtf2df4,f9D[dregc]--(double)F[frega]Convertssingleprecisionfloattodouble.cvtf2iEx:cvtf2if3,f4F[fregc]--(int)F[frega]Convertssingleprecisionfloattointeger.cvti2dEx:cvti2df2,f9D[dregc]--(double)F[frega]Convertsasignedintegertodoubleprecisionfloat.cvti2fEx:cvti2ff2,f5F[fregc]--(float)F[frega]Convertsasignedintegertosingleprecisionfloat.divEx:divf2,f2,f3F[fregc]--F[frega]/F[fregb]Allaresignedintegers.divdEx:divdf4,f4,f6D[dregc]--D[drega]/D[dregb]Allaredoubleprecisionfloats.divfEx:divff2,f3,f6F[fregc]--F[frega]/F[fregb]Allaresingleprecisionfloats.divuEx:divuf2,f3,f4F[fregc]--F[frega]/F[fregb]Allareunsignedintegers.eqdEx:eqdf2,f4if(D[drega]==D[dregb])fps=1elsefps=0Botharedoubleprecisionfloats.eqfEx:eqff3,f5if(F[frega]==F[fregb])fps=1elsefps=0Botharesingleprecisionfloats.gedEx:gedf8,f6if(D[drega]=D[dregb])fps=1elsefps=0Botharedoubleprecisionfloats.gefEx:geff3,f6if(F[frega]=F[fregb])fps=1elsefps=0Botharesingleprecisionfloats.gtdEx:gtdf8,f6if(D[drega]D[dregb])fps=1elsefps=0Botharedoubleprecisionfloats.gtfEx:gtff3,f6if(F[frega]F[fregb])fps=1elsefps=0Botharesingleprecisionfloats.jEx:jlabelPC--PC+imm26+4UnconditionallyjumpsrelativetothePCofthenextinstruction.imm26isa26-bitsignedinteger.jalEx:jallabelR31--PC+8;PC--PC+imm26+4Savesareturnaddressinregister31andjumpsrelativetothePCofthenextinstruction.imm26isa26-bitsignedinteger.jalrEx:jalrr2R31--PC+8;PC--R[rega]Savesareturnaddressinregister31anddoesanabsolutejumptothetargetaddresscontainedinR[rega].jrEx:jrr3PC--R[rega]R[rega]istreatedasanunsignedinteger.Doesanabsolutejumptothetarget