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modulecounts32(A,B,ALUctr,Result,Zero,Overflow);input[31:0]A,B;input[2:0]ALUctr;output[31:0]Result;outputZero,Overflow;wire[31:0]Result,t1,t2,t3;wireOverflow,Zero;wire[30:0]t4;wire[31:0]m,n;assignm={32{1'b0}};assignn={32{1'b1}};wireSUBctr,OVctr,SIGctr;wire[1:0]OPctr;wireAdd_carry,Add_Overflow,Add_Sign;wire[31:0]Add_Result;wire[31:0]temp1,temp2,temp6;wiretemp3,temp4,temp5;assignSUBctr=ALUctr[2];assignOVctr=!ALUctr[1]&ALUctr[0];assignSIGctr=ALUctr[0];assignOPctr[1]=ALUctr[2]&ALUctr[1];assignOPctr[0]=!ALUctr[2]&ALUctr[1]&!ALUctr[0];assigntemp1=B^{32{SUBctr}};addsa(A,temp1,SUBctr,Add_carry,Add_Overflow,Add_Sign,Add_Result,Zero);assigntemp3=SUBctr^Add_carry;assigntemp4=Add_Overflow^Add_Sign;assignt1={32{temp3}};assignt2={32{temp4}};twostt1(t1,t2,SIGctr,t3);assign{temp5,t4}=t3;twostt2(m,n,temp5,temp6);assigntemp2=A|B;threest(Add_Result,temp2,temp6,OPctr,Result);assignOverflow=Add_Overflow&OVctr;endmodulemoduleadds(A,B,Cin,Add_carry,Add_Overflow,Add_Sign,Add_Result,Zero);input[31:0]A,B;inputCin;output[31:0]Add_Result;outputAdd_carry,Add_Overflow,Add_Sign,Zero;reg[31:0]Add_Result;regAdd_carry,Add_Overflow,Add_Sign,Zero;always@(A,B,Cin)begin{Add_carry,Add_Result}=A+B+Cin;Add_Overflow=(Add_carry^A[31]^B[31]^Add_Result[31]);Add_Sign=Add_Result[31];if(Add_Result==8'h00000000)Zero=1'b1;elseZero=1'b0;endendmodulemodulethrees(A,B,C,OPctr,Result);input[31:0]A,B,C;input[1:0]OPctr;output[31:0]Result;reg[31:0]Result;always@(OPctr)case(OPctr)2'b00:Result=A;2'b01:Result=B;2'b10:Result=C;endcaseendmodulemoduletwos(A,B,ctr,out);inputctr;parameterj=32;input[j-1:0]A,B;output[j-1:0]out;reg[j-1:0]out;always@(ctr)case(ctr)1'b0:out=A;1'b1:out=B;endcaseendmodule