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moduleram_top(hclk,hresetn,hsel_s,haddr_s,hburst_s,htrans_s,hrdata_s,hwdata_s,hwrite_s,hready_s,hresp_s);inputhclk;inputhresetn;inputhsel_s;input[19:0]haddr_s;input[2:0]hburst_s;input[1:0]htrans_s;input[31:0]hwdata_s;inputhwrite_s;output[1:0]hresp_s;output[31:0]hrdata_s;outputhready_s;wire[31:0]ram_rdata;wire[17:0]ram_addr;wire[31:0]ram_wdata;wireram_write;ram_ahbifU_ram_ahbif(.hclk(hclk),.hresetn(hresetn),.hsel_s(hsel_s),.haddr_s(haddr_s),.hburst_s(hburst_s),.htrans_s(htrans_s),.hrdata_s(hrdata_s),.hwdata_s(hwdata_s),.hwrite_s(hwrite_s),.hready_s(hready_s),.hresp_s(hresp_s),.ram_rdata(ram_rdata),.ram_addr(ram_addr),.ram_wdata(ram_wdata),.ram_write(ram_write));ram_inferU_ram_infer(.q(ram_rdata),.a(ram_addr),.d(ram_wdata),.we(ram_write),.clk(hclk));endmodulemoduleram_infer(q,a,d,we,clk);output[31:0]q;input[31:0]d;input[17:0]a;inputwe;inputclk;reg[31:0]mem[262143:0];always@(posedgeclk)beginif(we)beginmem[a]=d;endendassignq=mem[a];endmodulemoduleram_ahbif(hclk,hresetn,//ahbslavehsel_s,haddr_s,hburst_s,htrans_s,hrdata_s,hwdata_s,hwrite_s,hready_s,hresp_s,//raminterfaceram_rdata,ram_addr,ram_wdata,ram_write);/////////////////////////////////////////declarationofinput&output///////////////////////////////////////inputhclk;inputhresetn;//ahbslaveinterfaceinputhsel_s;input[19:0]haddr_s;input[2:0]hburst_s;input[1:0]htrans_s;input[31:0]hwdata_s;inputhwrite_s;output[1:0]hresp_s;output[31:0]hrdata_s;outputhready_s;//raminterfaceinput[31:0]ram_rdata;output[17:0]ram_addr;output[31:0]ram_wdata;outputram_write;/////////////////////////////////////////declarationofregisters&wires///////////////////////////////////////wire[1:0]hresp_s;wire[31:0]hrdata_s;reghready_s;wire[31:0]ram_wdata;reg[17:0]ram_addr;regram_write;wirewr_en;wirerd_en;wireready_en;/////////////////////////////////////////program&function///////////////////////////////////////assignhresp_s=2'b00;always@(posedgehclkornegedgehresetn)begin//hsize=3'b010--32bitsif(!hresetn)beginram_addr=18'b000000000000000000;endelseif(hsel_s==1'b1)beginram_addr=haddr_s[19:2];endendassignwr_en=hsel_s&htrans_s[1]&hwrite_s;//assignrd_en=hsel_s&htrans_s[1]&!hwrite_s;always@(posedgehclkornegedgehresetn)beginif(!hresetn)beginram_write=1'b0;endelseif(wr_en)beginram_write=1'b1;endelsebeginram_write=1'b0;endendassignram_wdata=hwdata_s;assignhrdata_s=ram_rdata;assignready_en=hsel_s&htrans_s[1];always@(posedgehclkornegedgehresetn)beginif(!hresetn)beginhready_s=1'b0;endelseif(ready_en)beginhready_s=1'b1;endelsebeginhready_s=1'b0;endendendmodule