A-10-b-50-MS-820-SAR-ADC-With-On-Chip-Digital-Cali

410IEEETRANSACTIONSONBIOMEDICALCIRCUITSANDSYSTEMS,VOL.4,NO.6,DECEMBER2010A10-b50-MS/s820-WSARADCWithOn-ChipDigitalCalibrationMasatoYoshioka,KiyoshiIshikawa,TakeshiTakayama,andSanrokuTsukamoto,Member,IEEEAbstract—This10-b50-MSamples/sSARanalog-to-digitalcon-verter(ADC)featureson-chipdigitalcalibrationtechniques,com-paratoroffsetcancellation,acapacitordigital-to-analogconverter(CDAC)linearitycalibration,andinternalclockcontroltocom-pensateforPVTvariations.Asplit-CDACreducestheexponen-tialincreaseinthenumberofunitcapacitorsneededandenablestheinputloadcapacitancetobeassmallasthenoisere-striction.Theprototypefabricatedin65nm1P7Mcomplementarymetal–oxidesemiconductorwithMIMcapacitorachieves56.6dBSNDRat50-MSamples/s,25-MHzinputfrequencyandconsumes820Wfroma1.0-Vsupply,includingthedigitalcalibrationcir-cuits.Thefigureofmeritwas29.7fJ/conversion-stepundertheNyquistcondition.TheADCoccupiedanactiveareaof0.039mm.IndexTerms—Analog-to-digitalconverter(ADC),digitalcali-bration,successiveapproximationregister.I.INTRODUCTIONASYSTEM-ON-CHIP(SoC)forultrasoundsystemsandsensorsneedstwoormoreanalog-to-digitalconverters(ADCs)formultichannelinputs.Powerandareareductionsareveryimportantsincetheyenablemorechannelstobeimplementedinonechip.Reductionofthenumberofchipsresultsinaminiaturizationofthesystem.TechnologyscalingimprovesthedigitalperformanceofSoC,enablinglarge-scaleon-chipintegrationandhigh-speedoperationwithsuperiorenergyefficiency.Ontheotherhand,thepoorperformanceofthemetal–oxidesemiconductorfield-effecttransistors(MOS-FETs)inthesaturationregionmakesitdifficulttodesignahighgainamplifier,andthelowerpower-supplyvoltageintensifiesfloatingswitchandthermalnoiseproblems.Asaresult,itissteadilybecomingmoredifficulttodesignpipelinedADCsbecausetheADC’sperformancedependsontheamplifier’sperformance.Inaddition,atalowersupplyvoltage,theanalogsignalsuffersfromtheincreasedresistanceoftheanalogswitches.Successiveapproximationregister(SAR)ADCsaremorecompatiblewithtechnologyscalingbecausetheydonotneedoperationalamplifiersandhavefewerfloatingswitches.Theonlyanalogpartisthecomparator,whosedesignisclosetothatofadigitalregenerativelatch.ThismeansthatManuscriptreceivedJune11,2010;revisedSeptember12,2010;acceptedSeptember20,2010.DateofpublicationNovember09,2010;dateofcurrentversionNovember24,2010.ThispaperwasrecommendedbyAssociateEditorA.Hamoui.M.Yoshioka,K.Ishikawa,andS.TsukamotoarewithFujitsuLaboratoriesLtd.,Kawasaki,Kanagawa211-8588,Japan(e-mail:[e-mail];[e-mail];[e-mail]).T.TakayamaiswiththeFujitsuVLSILtd.,Kasugai,Aichi487-0013,Japan(e-mail:[e-mail]).Colorversionsofoneormoreofthefiguresinthispaperareavailableonlineatflowsifchargeleakagefromthecapacitordigital-to-analogconverter(CDAC)canbeavoided;hence,thepowerconsumptionwillbealinearfunctionoftheconversionrate.Infact,alow-powerpipelinedADCthatdoesnotrequireamplifiershasbeendeveloped[1].However,thepipelinearchi-tecturehasmorecircuitsthantheSARarchitecture.Hence,anSARarchitecturewouldstillbeabetterchoiceforlow-powerandcompactADCs.DesigningtheADCusingsmalldevicestakesadvantageofthescalingmerits.Higherconversionrateandsmallerareaaredirectbenefits.Smallerareainturncontributestoreducingthepowerconsumption,becausethesmallerparasiticsreducetherequireddrivepower.However,accuracysuffersfromdevicemismatch.Manydigitallyassistedtechniqueshavebeenreportedinanattempttoresolvethisissue.Foregroundcalibrationwasreported[2]asawaytoalignthemismatchofthecapacitors,buttheactualcalibrationwasdoneviaoff-chipsoftwareprocessing.AnonbinaryCDACdesignbasedonunitcapacitors[3]hasredundancyforcorrectingthemisjudgmentsofthecomparatorand/orincompleteCDACsettling.However,thelinearityisstillaffectedbycapacitormismatch.Nonbinarydesignsusing-CDACsarereportedin[4].Redundancyworksbecausetheupperbitdecisioncanhavealargerredun-dancy.However,thisstructureneedsadditionalstagesaswellasdigitalpostprocessing.Anothernonbinarydesign1.86wasimplementedwithindividuallyarrangedcapacitorswhichcanmaintainlinearitybyusingtheperturbationtech-nique[5].Thistechniquecancorrectthemismatchoftheradixbetweeneachbit.However,italsoneedsadditionalstagesanddigitalpostprocessing.Thispaperpresentson-chipdigitalcalibrationtechniquestocorrecttheCDACmismatchesbasedon[2]andaninternalclockcontrolthatenablesaveryslowconversionratewhileavoidingthechargeleakageproblemoftheCDAC.SectionIIdescribesthedesignandarchitectureoftheproposedSARADC.Sec-tionIIIpresentsthecalibrationtechniquesandSectionIVshowstheexperimentalresults.ConclusionsaregiveninSectionV.II.CIRCUITDESIGNA.ADCArchitectureFig.1showstheblockdiagramoftheSARADC.Theactualdesignisdifferential,butthefigureshowsasingle-endeddesignforsimplicity.Itconsistsofa10-bsplit-CDAC,acomparator,aninternalclockgenerator,SARcontroller,andadigitalcali-brationcircuit.Thesplit-CDACcanreducethenumberofunitcapacitorsrelativetoaconventionalbinaryweightedCDACde-sign;however,itisverysensitivetomi