FM0编码及其在FPGA中的设计与实现

ELECTRONICMEASUREMENTTECHNOLOGY32220092FM0FPGA昝勇1黎明1杨小芹1杨舸2张怡2(1.南昌航空大学南昌330063;2.西北工业大学电子信息学院西安710072):FM0FM0,,ALTERAQuartus,:FM0;;;:TN919.3:ADesignandimplementationofFM0codebyFPGAZanYong1LiMing1YangXiaoqin1YangGe2ZhangYi2(1.NanchangHangkongUniversity,Nanchang330063;2.SchoolofElectronicsandInformation,NothwesternPolytechnicalUniversity,Xian710072)Abstract:ThispaperdesignsandaccomplishesFM0codealgorithm,whichhasapplicationinshortdistancecommunicationwidely.Thepaperpresentsencoding/decodingalgorithmsdetailedlogicarchitecturebasedonFM0algorithm.ThenthepaperpresentstheactualtestresultsinQuartusIIsoftware.Thesimulatingresultsprovethedesignissimple,conciseandreliable,whichadaptsprogrammablelogicchipswell.Keywords:FM0code;shortdistancecommunication;PLD;dataencode0[13],,,HDB3FM0FM0FM0:T()0,,(1):ak=ak-1dk=0ak-1dk=1;kakdk=1;k(1)1CLK:;DIN:;CODE:;,FM0,FPGA11FM0,0T,2,DIN,TCLK4,OUTfpspdout,44,,0;0,0,T,9532电子测量技术22FM0,:0,13,RDIN,RCLK16,DEOUT,CLKOid1id2testclrclkbclkcclkd3,,16,FM0,16,id1,(clr),,8clkc2CLKO;4clkbid1,id2,test,CLKOtest,0,,FM0,0,DEOUT0;,1,96昝勇等:FM0编码及其在FPGA中的设计与实现2,FM01,DEOUT1,3ALTERAQuartus[47](OUTRDIN,RDINOUT);DIN,TCLK4RCLK16416(,),4()4,,RCLK16,,FM0,,1320,1320,28,20,clr,1320,clkbclkcCLKO,1320-18.75%+25%,[8]4,,,[1],,.[M].:,2005.[2]JT/T4622001[Z].[3].[2000]463,[M].[4]CPLDFPGA[J].,2006,27:24022404.[5].DSP[M].:,2001.[6].DSP+FPGA[J].,2007,28(5):918922.[7].DSP[J].,2005,19(6):3134.[8]TektronixRFIDNFC[M/OL].