微电子学概论

SJTUSJTU傅宇卓等上海交通大学微电子学院SJTUSJTUoutlinepCourseviewpSemiconductortechnologyviewpcurriculumviewpMoore’sLawpGreatPersons，GreatHistorypSemiconductorindustrySJTUSJTUIntroductionofthecoursepName：IntroductiononMicroelectronicspCourseNo：F210511presponsibility：SOMEptype：fundamentalcoursepmajor：ICDesign,SystemDesign,SemiconductorDeviceandfabricationpCredithours：36hoursSJTUSJTUContactinformationpInstructorspTeachingAssistant:xiangbenpEmail:[e-mail]:p(24p)pChooseimportantissuesandfocusonthempConsultsomeofthereferencesinthepresentedpaperpMinimizetheoverlapwithpreviouspresentationsandpattempttocoordinatewiththeotherpresenterSJTUSJTUCourseGradingpAttendance15%phomework35%pPaper30%pPresentation20%SJTUSJTUoutlinepCourseviewpSemiconductortechnologyviewpcurriculumviewpMoore’sLawpGreatPersons，GreatHistorypSemiconductorindustrySJTUSJTUWhatisSemiconductor电子p微电子技术（Microelectronics）即微型电子技术，集成电路是微电子技术的产物，是现代电子技术的根本SJTUSJTUChipInsideSJTUSJTUICClassificationSJTUSJTUWhatissystempEmbeddedsystempDriversoferpOS/CompilerpApplication(Video/Audio,DSPalgorithm,vision,recognision,controller,communicaiton,etc.)pComponentintegrationpIPintegrationSJTUSJTUPLLA/DD/AClockControllerJTAGUARTMCUMMUI2CCPUKeyboardI/FUSBControllerLCDControllerDMAControllerMemoryControllerOSCEmbeddedMemoryPLLA/DD/AClockControllerJTAGUARTMCUMMUI2CCPUKeyboardI/FUSBControllerLCDControllerDMAControllerMemoryControllerOSCEmbeddedMemory主板台式计算机CPUCPU硅工艺制造IC版图MOS晶体管铜互连集成电路(IC)领域ICpositioninsystemSJTUSJTUICDesignFlowSJTUSJTUESLDesignMethodologypEnsuresproperSoCarchitecturepriortofunctionalimplementationpPromotesIPreusebetweendesignsandbetweendesignstagesRequirementsCaptureSystemImplementationSystemValidationFunctionalImplementationFunctionalVerificationTraditionalNetlisttoGDSIIReuseSystemBlocksAsPlaceholdersReuseValidatingSW&ValidationSystemBlocksHandoffoftheExecutableSpecificationCreationofPlatformPrototypesSystemCVerilog/VHDLText/FSM/MatLabElectronicSystemLevelDesignSJTUSJTUSystemandMulti-CoreDebuggingLISADSPISSLISAµCISSSystemCBusModelExternalMemoryModelLogicInternalMemoryInternalMemoryArbiterSystemCPlatform•Debugandprofile(multiple)LISATekISSinasystemConnectionConnectionConnectionConnectionSJTUSJTUoxidationopticalmaskprocessstepphotoresistcoatingphotoresistremoval(ashing)spin,rinse,dryacidetchphotoresiststepperexposuredevelopmentTypicaloperationsinasinglephotolithographiccycle(from[Fullman]).SemiconductorManufactureSJTUSJTUImprovedbatterylifeSleekerformfactorLower-pricedhandsetsToday’sCellPhoneDSPRAMFLASHRadioAnalogPowerManagementPassivesDiscretes1/2thecost1/2thepower1/2theareaIntegrationinAction:DRPTMEnablesSingle-ChipCellPhoneSJTUSJTU90-nmCMOSprocess~90milliontransistorsDeliversCIFandVGAdisplay4megapixelstillimagingDolbyTM-qualityaudio3DaudioeffectsUptoDVD-qualityvideo3Dinteractivegaming\TVoutputDigitalTVreceptionImagingVideoAccelerator(IVA)2D/3DGraphicsAcceleratorARM11TMS320C55x™DSPOMAP2420SharedMemoryController/DMATimers,InterruptController,RTCInternalSRAM,Boot/SecureROMSecurity:SHA-1/MD5DES/3DESRNGAES,PKA,SecureWDT,KeysSPI1EACACUSBOTGTVOut(DAC)DisplayControllerMcBSPUARTEACMDEACBTUARTHigh-SpeedWLANa/b/gUART/IrDATraceJTAG/EmulationI/FGPMCSDRCI2CKeypadGPIOGPIOCameraI/FSerialParellelHDQ/1WireSystemInterfacePowerResetClockMgrMemoryStickMMC-SDPowerI2CSPI2All-in-OneEntertainmentArchitectureforCellPhonesSJTUSJTUFabrication&PackagingpTapeoutfinallayoutpFabricationp6,8,12”waferspOptimizedforthroughput,notlatency(10weeks!)pCutintoindividualdicepPackagingpBondgoldwiresfromdieI/Opadstopackage22SJTUSJTUProcessed8-inchwaferSJTUSJTU24TestingpTestthatchipoperatespDesignerrorspManufacturingerrorspAsingledustparticleorwaferdefectkillsadiepYieldsfrom90%to10%pDependsondiesize,maturityofprocesspTesteachpartbeforeshippingtocustomerSJTUSJTUStagesofICFabrication25WaferPreparationincludescrystalgrowing,rounding,slicingandpolishing.AssemblyandPackaging:Thewaferiscutalongscribelinestoseparateeachdie.Metalconnectionsaremadeandthechipisencapsulated.WaferFabricationincludescleaning,layering,patterning,etchinganddoping.Test/Sortincludesprobing,testingandsortingofeachdieonthewafer.FinalTestensuresICpasseselectricalandenvironmentaltesting.Defectivedie1.2.3.ScribelineAsingledieAssemblyPackaging4.5.WafersslicedfromingotSinglecrystalsiliconSJTUSJTUCMOSProcessFlowpOverviewofAreasinaWaferFabpDiffusionpPhotolithographypEtchpIonImplantpThinFilmspPolish26SJTUSJTUTraditionalAssemblyandPackaging27WaferTestandSortWireBondDieSeparationPlasticPackageFinalPackageandTestDieAttachSJTUSJTUTypicalICPackages28Quadflatpack(QFP)Leadlesschipcarrier(LCC)Plasticleadedchipcarrier(PLCC)Dualin-linepackage(DIP)Thinsmalloutlinepac