JESD22-A117C

JEDECSTANDARDElectricallyErasableProgrammableROM(EEPROM)Program/EraseEnduranceandDataRetentionStressTestJESD22-A117C(RevisionofJESD22-A117B,March2009)OCTOBER2011JEDECSolidStateTechnologyAssociationNOTICEJEDECstandardsandpublicationscontainmaterialthathasbeenprepared,reviewed,andapprovedthroughtheJEDECBoardofDirectorslevelandsubsequentlyreviewedandapprovedbytheJEDEClegalcounsel.JEDECstandardsandpublicationsaredesignedtoservethepublicinterestthrougheliminatingmisunderstandingsbetweenmanufacturersandpurchasers,facilitatinginterchangeabilityandimprovementofproducts,andassistingthepurchaserinselectingandobtainingwithminimumdelaytheproperproductforusebythoseotherthanJEDECmembers,whetherthestandardistobeusedeitherdomesticallyorinternationally.JEDECstandardsandpublicationsareadoptedwithoutregardtowhetherornottheiradoptionmayinvolvepatentsorarticles,materials,orprocesses.BysuchactionJEDECdoesnotassumeanyliabilitytoanypatentowner,nordoesitassumeanyobligationwhatevertopartiesadoptingtheJEDECstandardsorpublications.TheinformationincludedinJEDECstandardsandpublicationsrepresentsasoundapproachtoproductspecificationandapplication,principallyfromthesolidstatedevicemanufacturerviewpoint.WithintheJEDECorganizationthereareprocedureswherebyaJEDECstandardorpublicationmaybefurtherprocessedandultimatelybecomeanANSIstandard.Noclaimstobeinconformancewiththisstandardmaybemadeunlessallrequirementsstatedinthestandardaremet.Inquiries,comments,andsuggestionsrelativetothecontentofthisJEDECstandardorpublicationshouldbeaddressedtoJEDECattheaddressbelow,orcall(703)907-7559or©JEDECSolidStateTechnologyAssociation20113103North10thStreetSuite240SouthArlington,VA22201-2107Thisdocumentmaybedownloadedfreeofcharge;howeverJEDECretainsthecopyrightonthismaterial.Bydownloadingthisfiletheindividualagreesnottochargefororreselltheresultingmaterial.PRICE:PleaserefertothecurrentCatalogofJEDECEngineeringStandardsandPublicationsonlineat!DON’TVIOLATETHELAW!ThisdocumentiscopyrightedbyJEDECandmaynotbereproducedwithoutpermission.Organizationsmayobtainpermissiontoreproducealimitednumberofcopiesthroughenteringintoalicenseagreement.Forinformation,contact:JEDECSolidStateTechnologyAssociation3103North10thStreetSuite240SouthArlington,VA22201-2107orcall(703)907-7559JEDECStandardNo.22-A117CPage1TestMethodA117C(RevisionofTestMethodA117B)ELECTRICALLYERASABLEPROGRAMMABLEROM(EEPROM)PROGRAM/ERASEENDURANCEANDDATARETENTIONSTRESSTEST(FromJEDECBoardBallotJCB-11-73,formulatedunderthecognizanceoftheJC-14.1SubcommitteeonReliabilityTestMethodandPackagedDevices.)1ScopeThisstresstestisintendedtodeterminetheabilityofanEEPROMintegratedcircuitoranintegratedcircuitwithanEEPROMmodule(suchasamicroprocessor)tosustainrepeateddatachangeswithoutfailure(program/eraseendurance)andtoretaindatafortheexpectedlifeoftheEEPROM(dataretention).ThisStandardspecifiestheproceduralrequirementsforperformingvalidenduranceandretentiontestsbasedonaqualificationspecification.Enduranceandretentionqualificationspecifications(forcyclecounts,durations,temperatures,andsamplesizes)arespecifiedinJESD47ormaybedevelopedusingknowledge-basedmethodsasinJESD94.Thisstresstestdoesnotreplaceotherstresstestqualificationrequirements.Theprogram/eraseenduranceanddataretentiontestforqualificationandmonitoring,usingtheparameterlevelsspecifiedinJESD47,isconsidereddestructive.Lessertestparameterlevels(e.g.,oftemperature,numberofcycles,retentionbakeduration)maybeusedforscreeningaslongastheseparameterlevelshavebeenverifiedbythedevicemanufacturertobenondestructive;thiscanbeperformedanywherefromwaferleveltofinisheddevice.2Termsanddefinitions2.1EEPROMAreprogrammableread-onlymemoryinwhichthecellsateachaddresscanbeerasedelectricallyandreprogrammedelectrically.NOTEThetermEEPROMinthisdocumentincludesallsuchmemories,includingFLASHEEPROMintegratedcircuitsandembeddedmemoryinintegratedcircuitssuchasErasableProgrammableLogicDevices(EPLDs)andmicrocontrollers.Destructive-readmemoriessuchasferroelectricmemories,inwhichthereadoperationre-writesthedatainthememorycells,arebeyondthescopeofthisdocument.2.2DatapatternThemixof1sand0sinthememoryandtheirphysicalorlogicalpositions.NOTEAdevicemaybesingle-bit-per-cell(SBC),meaningthatonephysicalmemorycellstoresa“0”ora“1”,ormultiple-bits-per-cell(MBC),meaningthatonecellstorestypicallytwobitsofdata:“00”,“01”,“10”,or“11”.InsomeMBCmemories,thetwobitsrepresentlogically-adjacentbit-pairsineachbyteofdata.Forexample,abytecontainingbinarydata10110001wouldcorrespondtofourphysicalcellswithdata2301inbase-fourlogic.InotherMBCmemories,thetwobitsmayrepresentbitsinentirelydifferentaddresslocations.ForanSBCmemoryaphysicalcheckerboardpatternconsistsofalternating0sand1s,witheach0surroundedby1soneithersideandaboveandbelow;alogicalcheckerboardpatternconsistsofdatabytesAAHor55Hinwhicheach0islogicallyadjacentto1s.Insomequalificationsonlylogicalpositionsmaybeknown.JEDECStandardNo.22-A117CPage2TestMethodA117C(RevisionofTestMethodA117B)2.