基于VerilogHDL的ADC0809采样控制器设计

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2020-06-10

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200612InformationTechnology:TP331:A:1009-2552(2006)12-0151-03VerilogHDLADC08091,2,3(1.,210096;2.,226007;3.,150001):ADC0809VerilogHDLADC0809,Quartus4.0,AlteraCPLDEP1K30TC144-3GW48EDAA/D:ADC0809;VerilogHDL;Quartus4.0DesignofADC0809samplingcontrollerbasedonVerilogHDLWANGZhi2liang1,2,LIGuang2hui3(1.SoutheastUniversity,Nanjing210096,China;2.NantongUniversity,Nantong226007,China;3.HeilongjiangCreditlnformationCentre,Harbin150001,China)Abstract:Inthispaper,theprincipleofADC0809isintroducedatfirst,thenhowtodesignADC0809sam2plingcontrollerbasedonVerilogHDLisstated,andthecircuitsfunctionsimulationwaveformonQuartus4.0isgiven,andatlastthecircuitisimplementedbyconfiguringtheAlteraCPLDdeviceEP1K30TC144-3andtheGW48EDAsystemforteachingandexperiments.ADC0809samplingcontrollerisprovedtobestableandreliable.Keywords:ADC0809;VerilogHDL;Quartus4.0ADC0809CMOS8APD,8,8ADC08098,8,,5VADC0809,APDADC08091ADCO8O98APDADC0809APD,1[1]ADCAPD,,,,DPAU018A/DADC0809,,ADC0809,:2006-07-05:(1978-),,,,151©1994-2008ChinaAcademicJournalElectronicPublishingHouse.Allrightsreserved.=1,DPAU0U0Ui,UiUo,1,D71;UiUo,0,D71,D6=1,DPAU0(3P41P4),Ui,1,,D0,8,8APD,,,,ADC08098APD,83,8[2],3,88APD,,,,;,ADC0809CMOS,,515V5V,05V,TTLADC080922ADC08092ADC0809ADC0809adc3d[7:0],eoc,oe,ale,startADC0809;reset,;q[7:0],ADC0809VerilogHDLAPD:moduleadc(d,clk,eoc,lock,ale,start,oe,adda,q,3reset);inputreset;input[7:0]d;inputclk,eoc;outputlock,ale,start,oe,adda;output[7:0]q;reg[7:0]q;regale,start,oe,adda;reg[2:0]currentstate,nextstate;reglock;PPparameterst0=3b000;parameterst1=3b001;parameterst2=3b010;parameterst3=3b011;parameterst4=3b100;parameterst5=3b101;parameterst6=3b110;PPalways@(currentstateoreoc)begincase(currentstate)st0:beginale=0;start=0;oe=0;lock=0;nextstate=st1;endst1:beginale=1;start=0;oe=0;lock=0;nextstate=st2;endst2:beginale=0;start=1;oe=0;lock251©1994-2008ChinaAcademicJournalElectronicPublishingHouse.Allrightsreserved.=0;nextstate=st3;endst3:beginale=0;start=0;oe=0;lock=0;!if(eoc==1)nextstate=st3;elsenextstate=st4;endst4:beginale=0;start=0;oe=0;lock=0;if(eoc==0)nextstate=st4;elsenextstate=st5;endst5:beginale=0;start=0;oe=1;lock=0;nextstate=st6;endst6:beginale=0;start=0;oe=1;lock=1;nextstate=st0;enddefault:beginale=0;start=0;oe=0;lock=0;nextstate=st0;endendcaseendPPalways@(posedgeclkorposedgereset)beginif(reset)begincurrentstate=0;adda=1;endelsecurrentstate=nextstate;endPPalways@(posedgelock)beginq=d;endendmodulecase[3],,,,,[4]3Quartus4.0ADC08093Quartus4.0,AlteraCPLDEP1K30TC144-3,GW48EDA,ADC0809,3,EDA,CPLDADC0809,:[1].80X86[M].,1995.[2].[M].,1999.[3],.VerilogHDL[M].,2005.[4].VerilogHDL[M].,1998.:351©1994-2008ChinaAcademicJournalElectronicPublishingHouse.Allrightsreserved.