EP9142-UG-V01

Explorereservestherighttomakechangeswithoutfurthernoticetoanyproductshereintoimprovereliability,functionordesign.Exploredoesnotassumeanyliabilityarisingoutoftheapplicationoruseofanyproductorcircuitdescribedherein;neitherdoesitconveyanylicenseunderitspatentrightsnortherightsofothers.Exploreproductsarenotdesigned,intended,orauthorizedforuseascomponentsinsystemsintendedforsurgicalimplantintothebody,orotherapplicationsintendedtosupportorsustainlife,orforanyotherapplicationinwhichthefailureoftheExploreproductcouldcreateasituationwherepersonalinjuryordeathmayoccur.ShouldBuyerpurchaseoruseExploreproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdExploreanditsofficers,employees,subsidiaries,affiliates,anddistributorsharmlessagainstallclaims,costs,damages,andexpenses,andreasonableattorneyfeesarisingoutof,directlyorindirectly,anyclaimofpersonalinjuryordeathassociatedwithsuchunintendedorunauthorizeduse,evenifsuchclaimallegesthatExplorewasnegligentregardingthedesignormanufactureofthepart.UserGuide—EP9142_UGV0.1ExploreConfidentialProprietryNON-DISCLOSUREAGREEMENTREQUIRED1HDMI1.4SplitterEP9142UserGuideV0.1OriginalReleaseDate:May.12,2010ExploreRevised:Apr.26,2011惠东益顺电子厂UserGuide—EP9142_UGV0.1ExploreConfidentialProprietryNON-DISCLOSUREAGREEMENTREQUIRED2RevisionHistoryVersionNumberRevisionDateAuthorDescriptionofChanges0.0May/12/2010JerryChenInitialVersion0.1Apr/26/2011EtherLaiRevisePinSequence;AdddetailedPackageOutlineInformation;ReviseControlRegisterDescriptions;惠东益顺电子厂UserGuide—EP9142_UGV0.1ExploreConfidentialProprietryNON-DISCLOSUREAGREEMENTREQUIRED3Section1Introduction1.1OverviewEP9142isa2-PortDVI/HDMIsplitterwithintegratedHDCPdecryption/encryptionenginesandiscompliantwithHDMIRev1.4andHDCPRev1.3specifications.EP9142receivesDVI/HDMIinputs,processHDCPdecryptionandencryptionandtransmitsthedatato2DVI/HDMIports.1.2Features•DVISpecification1.0Compliant•HDMISpecification1.4aCompliant•IntegratedHDCPdecryption/encryptionengineswhicharecompliantwithHDCPRev1.3specification•WideFrequencyRange:25MHz-340MHz•Supports12-bitDeepFullHD,Full3Dand4K2Kvideo.•SupportsStandardAudio,DSDAudioandHD(HBR)Audio•Supports1DVI/HDMIinputportand2DVI/HDMIoutputports•SupportsconversionofHDMIsignalingtoDVIsignaling•SupportsHDCPRepeater•Cascadabletomakemorethan4outputports•64-PinTQFP(Pb-Free;E-PAD)惠东益顺电子厂UserGuide—EP9142_UGV0.1ExploreConfidentialProprietryNON-DISCLOSUREAGREEMENTREQUIRED4惠东益顺电子厂UserGuide—EP9142_UGV0.1ExploreConfidentialProprietaryNON-DISCLOSUREAGREEMENTREQUIRED5Section2Overview2.1BlockDiagramFigure2-1BlockDiagramDDC_SDADDC_SCLEXT_RSTbIICSlaveRegisters&LogicsDVI/HDMIReceiverEXT_SWINGHDCPKeysRX0+/-RX1+/-RX2+/-RXC+/-DVI/HDMITransmitterMCU_SDAMCU_SCLIICSlaveHDCPKeysDVI/HDMITransmitterHDCPKeysTX00+/-TX10+/-TX20+/-TXC0+/-TX01+/-TX11+/-TX21+/-TXC1+/-惠东益顺电子厂UserGuide—EP9142_UGV0.1ExploreConfidentialProprietaryNON-DISCLOSUREAGREEMENTREQUIRED62.2PinDiagramFigure2-216151413121110543211718192021222324252627283738394041424344454647486463626160595857565554539876333435362930313252515049TXC1+TXC1-TX01+AVSSTX11-TX11+AVDDTX21-TX21+AVSSAVSSPVSSPVDDTX01-AVDDCOMR0AVSSTX20+TX20-AVDDTX10+TX10-AVSSTX00+TX00-AVDDTXC0+TXC0-AVSSPVSSPVDDHT_PLG0HT_PLG1VSSVDDSCL3SDA3VSSEVDDESCL2SDA2SCL1SDA1EXT_RSTbVDDVSSA1COMR1PVSS/AVSSPVDD/AVDDRXC-RXC+AVSSRX0-RX0+AVDD33RX1-RX1+AVDDRX2-RX2+EXT_RESEXT_SWING0EXT_SWING1PinDiagram惠东益顺电子厂UserGuide—EP9142_UGV0.1ExploreConfidentialProprietaryNON-DISCLOSUREAGREEMENTREQUIRED72.3PinDescriptionUnlessotherwisestated,unusedinputpinsmustbetiedtoground,andunusedoutputpinsleftopen.Table2-1IICPinsNAMEIN/OUTDESCRIPTIONDDC_SCLINIICSCLsignalforreceiverportDDCDDC_SDAIOIICSDAsignalforreceiverportDDC(opendrain)EE_SCLOUTSCLinputforEEIICport.Connectthispinto4.7Kpullupresistor.(opendrain)EE_SDAIOSDAin/outforEE.Connectthispinto4.7Kpullupresistor.(opendrain)EE_WPTINWPT(writeprotect)inputforEE.Connectthispinto3.3VtopreventHDCPkeyloss.MCU_SCLINIICSCLsignalforinternalregistersaccessMCU_SDAIOIICSDAsignalforinternalregistersaccess(opendrain)A1,A0INDeterminethelowest2-bitoftheIICaddressforMCUIICportTable2-2Misc.PinsNAMEIN/OUTDESCRIPTIONEXT_RSTbINExternalReset(ActiveLOW).AHIGHlevelindicatesnormaloperationandaLOWlevelcausesallthelogiconthechiptobereset.V_OUTOUTPolaritycorrectedverticalsyncpulse(activehigh)derivedfromreceiverinputTable2-3ReceiverPinsNAMEIN/OUTDESCRIPTIONRX0-RX0+RX1-RX1+RX2-RX2+AnalogDifferentialDataInputPairsforreceiverportRXC-RXC+DifferentialClockInputPairsforreceiverportEXT_RESAnalogDVI/HDMIExternalTerminationResistorTable2-4TransmitterPinsNAMEIN/OUTDESCRIPTIONTX00-TX00+TX10-TX10+TX20-TX20+AnalogDifferentialDataOutputPairsfortransmitterport0TXC0-TXC0+DifferentialClockOutputPairsfortransmitterport0惠东益顺电子厂UserGuide—EP9142_UGV0.1ExploreConfidentialProprietaryNON-DISCLOSUREAGREEMENTREQUIRED8HTPLG0INHotPlugInputThispinisusedtomonitorthe“HOTPLUG”signalfortransmitterport0.Note:Thisinputisonly3.3Vtolerantandhasnointernaldebouncingcircuit.EXT_SWING0AnalogVoltageSwingAdjustfortransmitterport0.AresistorshouldtiethispintoAVDD18.Thisresist