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51.6.1RXEDGIFRxDS2[RXEDGIF]1RXEDGIFS2[RXEDGIF]1S2[RXEDGIF]RXEDGIES2[RXEDGIF]1)RxDS2[RXINV]S2[RXINV]0S2[RXINV]1RxDRxD10012)RXEDGIF1S2[RXEDGIF]RXEDGIFRxDRxD1S2[RXEDGIF]S2[RXEDGIF]3)()(S2[RXEDGIF]=1)CPU51.7DMAS1[TDRE]DMAS1[TDRE]DMA51-47DMA51-47DMADMATDRETIE=1TDMAS=1RDRFRIE=1RDMAS=1DMA1DMAS2[RDRF]DMAS1DDMADMADMADMADMA51.8UART51.8.1/UARTPFIFO[TXFIFOSIZE]PFIFO[RXFIFOSIZE]FIFO/PFIFO[RXFE]PFIFO[TXFE]()1.TXFIFO[TXWATER]0TDRES1[TC]2.TCFIFO[TXCOUNT]TCFIFO[TXCOUNT]=03.S1[TC]S1[TC]51.8.2ISO_7816ISO_7816UARTISO_7816UART1.UART(BDH/L)0BDHBDL7816()Fi=372Di=15MHzBDHBDLC41/3725MHz2.BDH[LBKDIE]=03.C1(LOOPSRSRC)C1[M]=1C1[PE]=1,C1[PT]=04.S2[RWUID]=0S2[LBKDE]=05.MODEM[RXRTSE]=0MODEM[TXRTSPOL]=0MODEM[TXRTSE]=0MODEM[TXCTSE]=06.(C3[ORIE],C3[NEIE],C3[PEIE]C3[FEIE])7.C4[MAEN1]=0C4[MAEN2]=08.C5DMA9.C7816[INIT]=1C7816[TTYPE]=0C7816[IOS_7816E]=1C7816[ONACK]C7816[ANACK]10.IE781611.ET781612.C2[ILIE]=0C2[RE]=1C2[TE]=1C2[RWU]=0C2[SBK]=0C2[TIE]C2[TCIE]C2[RIE]UARTS2[MSBF]C3[TXINV]S2[RXINV]C2[RE]=0C2[TE]=07816UART(C7816[TTYPE])C2[RE]C2[TE]51.8.2.1C7816[TTYPE]=0C7816[TTYPE]=0/S1[TDRE]()UARTC2[TE]=1TXDIR//FIFO51.8.2.2C7816[TTYPE]=1C7816[TTYPE]=1()TLENCRCTLENC2[TE]=1C2[RE]=1S1[TDRE]/TLEN()UARTC2[TE]0UARTy8ingg51.8.3(ISO_7816)UART1.UARTA.UART(BDH/L)0BDHBDLB.C1(LOOPS,RSRC,M,WAKE,ILT,PE,PT)C4MA1MA2C.C2(TIE,TCIE,RIE,ILIE,TE,RE,RWU,SBK)S2(MSBF,BRK13)C3(ORIE,NEIE,PEIE,FEIE)2.A.S1TDRES1[TDRE]TCFIFO[TXCOUNT]B.TDREC3[T8]/D3.21.C3[T8]/D2.S1[TDRE](TWFIFO[TXWATER]=0)3.C2[TE]4.()C3[T8]/D51.8.4(OR)S1[OR]S1[RDRF]S1[IDLE]S1[RDRF]S1[IDLE]51.8.4.1S1[OR]S1[OR]S1[OR]S1[OR]1.CFIFO[RXFLUSH]2.S1[OR]CFIFO[RXFLUSH]S1[OR]SFIFO[RXUF]S1[OR]FIFOORORSFIFO[RXUF]SFIFO[RXUF]C7816[ISO_7816E]C7816[TTYPE]=1C7816[ONACK]=1S1[OR]LIN(LBKDE)S1[OR]S1[OR]1LIN(S2[LBKDIF])S2[LBKDIF]LINS2[LBKDIF]51.8.5NACKC7816[ISO_7816E]C7816[TTYPE]=07816C7816[ONACK]NACK()NACKNACKNACKNACKET7816[RXTHRESHOLD]1S1[OR]51.8.651.8.751.8.7.1RTSRTSUARTCTSUARTTIA-232-EUARTRTSCTS51-59CTSRTS51.8.7.2RTS51-60RTSRS_485UARTUARTRTSRTS51-6051-60RTS_BDERE_BRXDRXDUARTRXD51.8.8IrDAIrDA1.6UART/1.6115.3Kb/s3/161.651.8.97816(WT,BWT,CWT)IS7816[WT]IS7816[BWT]IS7816[CWT]7816UART1.IS7816[WT]96002.9600WT3.IS7816[WT]97004.WT9701WT51.8.10UART1.(MAFBM10)2.3.S1[OR]1S1[IDLE]4.(FIFO)S1[OR]1S1[RDRF]S1[OR]S1[RDRF]ORRDRF1C2[RWU]1(WAKE=0)IDLEC2[RWU]C2[RWU]1(WAKE=0)C2[RWU]53I2SI2SI2SDSPsinter‐IC sound I2SIntel® AC97I2SI2S53.1.1 I2S:FIFOTxRx FIFO FIFO53‐1 I2S53.1.2 I2S/FIFO FIFO15x32Tx/Rx FIFOI2S, lsb‐ and msb‐aligned 8, 10, 12, 16, 18, 20, 22 or 24I2SI2SSRCKAC97AC97I2SSRCKCPUI2S53.1.3 I2SI2SAC97AC97(ACNT[FV] = 0) AC97(ACNT[FV] = 1) I2STx,Rx TDMDSP TDMDSP SPIDSPMCU 53‐1 I2SI2SRCR[RXBIT0, RSHFD]I2SI/OI/O232I2S I2SRCCR[DC] TCCR[DC]I2S232I2SI2SAC97AC97AC97I2SI2SI2SI2SI2STCCR[DC] RCCR[DC]Detailed operang mode descripons-753‐2 I2SI/O SRCK SRCKSTCKI/O I/O SRFS SRFSSRFSSTCKSRCKSRFSI/O SRXD SRXDI STCK STCKSCTKI/O STFS STFSSTFSTSCKPSTCKSTFSTSCKPSTCKSTFSI/O STXD STXDSTXDSTXDO I2SSTFS SRFSTx/RxI2SRCR[RXDIR] = 1,TCR[TXDIR] = 1,RCR[RFDIR] = 1,TCR[TFDIR] = 1, CR[SYN] = 0 Tx/RxI2SRCR[RXDIR] = 0,TCR[TXDIR] = 0,RCR[RFDIR] = 0,TCR[TFDIR] = 0, CR[SYN] = 0RxI2SRCR[RXDIR] = 1, TCR[TXDIR] = 0,RCR[RFDIR] = 1,TCR[TFDIR] = 0, CR[SYN] = 0TxI2S TxI2SRCR[RXDIR] = 0, TCR[TXDIR] = 1, RCR[RFDIR] = 0, TCR[TFDIR] = 1, CR[SYN] = 0 RxI2S53‐2 SYN = 0I2S853‐3 53‐3 I2Shex/4002_F000 I2S0(I2S0_TX0) 32 R/W 0000_0000h53.3.1/ 1693 4002_F004 I2S1(I2S0_TX1) 32 R/W 0000_0000h53.3.2/ 1693 4002_F008 I2S0 (I2S0_RX0) 32 R 0000_0000h53.3.3/ 1694 4002_F00C I2S1 (I2S0_RX1) 32 R 0000_0000h53.3.4/ 1694 4002_F010 I2S(I2S0_CR) 32 R/W 0000_0000h53.3.5/ 1695 4002_F014 I2S(I2S0_ISR) 32 R/W 0000_3003h53.3.6/ 1698 4002_F018 I2S(I2S0_IER) 32 R/W 0000_3003h53.3.7/ 1703 4002_F01C I2S(I2S0_TCR) 32 R/W 0000_0200h53.3.8/ 1707 4002_F020 I2S(I2S0_RCR) 32 R/W 0000_0200h53.3.9/ 1709 4002_F024 I2S(I2S0_TCCR) 32 R/W 0004_0000h53.3.10/1711 4002_F028 I2S(I2S0_RCCR) 32 R/W 0004_0000h53.3.11/1713 4002_F02C I2S FIFO/(I2S0_FCSR) 32 R/W 0081_0081h53.3.12/1714 4002_F038 I2S AC97(I2S0_ACNT) 32 R/W 0000_0000h53.3.13/1720 4002_F03C I2S AC97(I2S0_ACADD) 32 R/W 0000_0000h53.3.14/1721 4002_F040 I2S AC97(I2S0_ACDAT) 32 R/W 0000_0000h53.3.15/1722 4002_F044 I2S AC97(I2S0_ATAG) 32 R/W 0000_0000h53.3.16/1722 4002_F048 I2S(I2S0_TMSK) 32 R/W 0000_0000h53.3.17/1723 4002_F04C I2S(I2S0_RMSK) 32 R/W 0000_0000h53.3.18/1723 4002_F050 I2S AC97(I2S0_ACCST) 32 R 0000_0000h53.3.19/1724 4002_F054 I2S AC97(I2S0_ACCEN) 32 W00000_0000h53.3.20/1724 4002_F058 I2S AC9732 W00000_0000h53.3.21/1725 53.3.1 I2S0(I2Sx_TX0) TX0I2SI2S0_TX04002_F000h+0h=4002_F000h I2Sx_TX0310 TX0 I2SI2STx FIFO(TXSR)FIFOTX0TX1TXSRTX1TXTX FIFO01‐16TX01611‐15 FIFO16TX FIFO012TX021I2SI2S(CR[I2SEN]=1) 53.3.2 I2S1(I2Sx_TX1) TX1I2SI2S0_TX14002_F000h+4h=4002_F004h I2Sx_TX1310 TX1 I2SI2STx FIFO(TXSR)FIFOTX0TX1TXSRTX1TXTX FIFO01‐16TX01611‐15 FIFO16TX FIFO012TX021I2SI2S(CR[I2SEN]=1) 53.3.3 I2S0 (I2Sx_RX0) RX0I2SI2S0_RX04002_F000h+8h=4002_F008h I2Sx_RX0310 RX0 I2SI2SRx FIFORXSRFIFORX153.3.4 I2S1 (I2Sx_RX1) RX1I2SI2S0_RX14002_F000h+Ch=4002_F00Ch I2Sx_RX1310 RX1 I2SI2S