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StevenShi(steven-shi@ti.com)TelecomAFATeamTexasInstrumentsHighSpeedLayoutConsiderations1)GeneralConsiderationsa)Models:Resistors,Capacitors,Inductors,andCircuitBoard2)HighSpeedOpAmpLayouta)Inputandoutputconsiderationsb)Signalroutingc)Bypasscapacitorsd)Layoutexamples3)HighSpeedADC/DACDesignandLayouta)Inputandoutputconsiderationsb)BypassCapacitorsc)SplittingtheGroundPlane4)HighSpeedClockLayoutGuidelinesa)Coupling(InterferenceorCrossTalk)b)PowerSupplyFilteringc)PowerSupplyBypassing&Groundingd)LayoutTrickstoReduceEMIAgendaHighSpeedLayoutKeyGeneralConsiderations¾Keypoints–Useshortdirectsignalrouting–Controlparasiticcapacitance–Useadequatelocalbypasscapacitors–Managegroundplanes–AvoidgroundloopsCESRESLCESRESLCNOM(Temp,Freq,Voltage)(Temp,Voltage)RLEAK(Voltage)CPAR.RPAR.()2CESL2)X(X(ESR)Z++=Ω()Lf2XESLπΩ=()Cf21XCπΩ=IdealModelBetterModelBestModelImpedanceVs.Frequency0.010.101.0010.001101001000Frequency-MHzImpedance-OhmsZ=2PifLZ=1/2PifCL=1nHC=0.01uFIdealCapacitorESLLimitationRealCapacitorLC21fRESπ=CapacitorModelsLDCRLIWCDCRLIWCRR(Freq,Temp)RPAR(Temp)IdealModelBetterModelBestModel()IWCLIWCLXXXXDCRZ++=Ω()Lf2XLπΩ=()Cf21XIWCπΩ=LC21fRESπ=ImpedanceVs.Frequency101001000100001101001000Frequency-MHzImpedance-OhmsZ=2PifLZ=1/2PifCL=1uHIWC=10pFIWCLimitationIdealInductorRealInductorInductorModelsRRLLEADCPackageRLLEADCPackage(Temp)IdealModelBetterModelBestModel¾UsingSMTresistorsminimizesleadinductancetothepointthatPCBtracesarethelimitingfactor¾SMTpackagesalsominimizethecapacitancebetweentheleadssuchthatthisparasiticisusuallyinsignificant¾NotethatresistorpacksCANhavesignificantleadinductanceandresistor-to-resistorcapacitance,sochoosewiselybasedontheapplication¾Resistorswillhavetemperaturecoefficients,200PPMiscommon,buthigherprecisionisavailable¾AVOIDWire-woundresistorsandleadedresistorsforhighspeedapplicationsduetotheirlargeinductanceResistorModelshtwεrD21h⎟⎠⎞⎜⎝⎛+×=hD1Ij(A/cm)Oπj(A/cm)IO=totalsignalcurrent(A)h=PCBthickness(cm)D=distancefromcenteroftrace(cm)¾ReturnCurrentFlowisdirectlybelowthesignaltrace¾MusthaveSolidreturnpath(i.e.SolidGroundPlane)underthesignaltraceforlowestimpedance.–Donotroutehighspeedsignalsnearedgeofboard;especiallyclocksRememberCurrentReturnPath⎟⎠⎞⎜⎝⎛+≈twhlnL(nH)0.85.982x()0.85.981.410.264x⎟⎠⎞⎜⎝⎛++≈twhlnrC(pF)εhtwεrComponent:MicrostripCopperTracesPurpose:InterconnecttwoormorepointsProblem:InductanceandCapacitancex=lengthoftrace(cm)w=widthoftrace(cm)h=thicknessofboard(cm)t=thicknessoftrace(cm)er=PCBdielectricconstant(FR-4≈4.5)0.8mm(0.031”)traceon0.8mm(0.031”)thickPCB(FR-4)has:≈4nHand0.8pFpercm≈10nHand2.0pFperinchL(nH)C(pF))ps/cm(Tp31.6=()C(pF)L(nH)Z031.6=ΩPCBComponents0.0886hC(pF)Arε≈Component:CopperPlanesPurpose:UsedForGroundPlanesandPowerPlanesProblem:StrayCapacitanceonSignalTracesBenefit:Athighfrequencies(1G+)AddsBypassCapacitancewithlowInductanceh=separationbetweenplanes(cm)A=areaofcommonplanes=l*w(cm2)er=PCBdielectricconstant(FR-4≈4.5)0.8mm(0.031”)thickPCB(FR-4)has:≈0.5pFpercm2≈32.7pFperinch2hεrwlAPCBComponents0.4mm(0.0157”)viawith1.6mm(0.063”)thickPCBhas≈1.2nH1.6mm(0.063”)Clearanceholearound0.8mm(0.031”)padonFR-4has≈0.4pFComponent:ViasPurpose:InterconnecttracesondifferentlayersProblem:InductanceandCapacitance⎥⎦⎤⎢⎣⎡⎟⎠⎞⎜⎝⎛+≈dhlnhL(nH)41512105550dddhC(pF)r−≈ε.er=PCBdielectricconstant(FR-4≈4.5)L(nH)C(pF))ps/cm(Tp31.6=()C(pF)L(nH)Z031.6=ΩPCBComponents1)GeneralConsiderationsa)Models:Resistors,Capacitors,Inductors,andCircuitBoard2)HighSpeedOpAmpLayouta)Inputandoutputconsiderationsb)Signalroutingc)Bypasscapacitorsd)Layoutexamples3)HighSpeedADC/DACDesignandLayouta)Inputandoutputconsiderationsb)BypassCapacitorsc)SplittingtheGroundPlane4)HighSpeedClockLayoutGuidelinesa)Coupling(InterferenceorCrossTalk)b)PowerSupplyFilteringc)PowerSupplyBypassing&Groundingd)LayoutTrickstoReduceEMIAgenda¾Invertinginputnodeofanopampissensitivetostraycapacitance(CSTRAY)¾RF,RGandCSTRAYaddazerotothenoisegainwhichcanleadtoinstability¾AsLittleas1pFofCSTRAYcancausestabilityproblems¾invertinginputNodeincludestheentiretraceuptotheplacementofRF,RG,andanyothercomponentontheinvertinginput(-)InputCapacitance()()GFSTRAYR||RC21×=πNG_ZEROfCSTRAYmodifiesthenoisegainbyaddingazeroOpenLoopGainindBNoiseGainwithIdealResistiveFeedbackFactorStabilityisdeterminedbyrateofclosurebetweenopenloopgainandnoisegainFrequencyinHz-20dB/decNoiseGainwithcapacitanceoninvertinginputBodePlot(-)InputCapacitanceisBadNoissueifthezerofallstorightofa(f)intersectiona(f)NoiseGainRateofclosure=40dB/dec=NotStableRateofclosure=20dB/dec=Stable()()GFSTRAYR||RC21×=πNG_ZEROfSolutions:1.EliminateGroundPlanesandPowerPlanesunderandneartheinvertinginput(-)2.Shortentracebymovingcomponentsclosertotheinvertinginput(-)3.ReduceRFandRGvalues4.Increasenoisegainofopamp5.PlaceCompensationCapacitorAcrossRF6.UseInvertingConfigurationInvertingConfigurationMinimizingStrayCat(-)Input+-VINRFRGRTERMRLOADCSTRAYVRORNCNIncreaseNoiseGainFeedbackCapCompensationSTRAYFGCOMPCRRC=OSTRAY_POLEARC21fOLπ≈Assuming:RORF,RLOAD¾Opampsaresensitivetocapacitanceonoutput(CSTRAY)¾RealopampshaveoutputImpedance(RO)¾ROandCSTRAYcr