基于DSP(DM642)的嵌入式人脸识别器的设计

上海交通大学硕士学位论文基于DSP（DM642）的嵌入式人脸识别器的设计姓名：皮小平申请学位级别：硕士专业：集成电路设计与制造指导教师：祝永新20061210DSPDM642DSPDM642DM642DMAABSTRACTDesignofanEmbeddedSystemofHumanFaceRecognitionABSTRACTThispaperpresentsanembeddedsystemoffacerecognitionfromtheactualrequirements,whichincludeframework,hardware(Circuitanddriver)andsoftware.Theframeworkchapteranalyzestherequirementsofsystemandmakesachoiceaboutembeddedprocessor(DSP).ThehardwarechapterintroducestheexternalmemorymoduleandvideoI/Omodule,programsvideo-driverfortheDM642byusingCSL,discusstheapplicationsofinterruptanddirectmemoryaccess(DMA).Thesoftwarechapterintroducestheprincipleoffacerecognitionalgorithm,anddiscussestheproblemsofalgorithmoptimizationandsoftwareporting.KEYWORDS:EmbeddedSystem,DigitalSignalProcessor(DSP),FaceDetection,FaceRecognition78AdaBoostAdaptiveBoostingCSLChipSupportLibraryCVBSCompositeVideoBurstSyncDMADirectMemoryAccessEAVEndOfActiveVideoEMACEthernetMediaAccessControllorESLEquivalentSeriesInductanceESREquivalentSeriesResistanceFIRFiniteImpulseResponseISFPInterruptServiceFetchPacketISTInterruptServiceTableISTPInterruptServiceTablePointLDALinearDiscriminantAnalysisPCAPrincipleComponentAnalysisSAVStartOfActiveVideoTCCTransferCompleteCodeTSITransportStreamInterface8283111888GaltonNature1965Chan&BledsoePanoramicResearchIn1.1BiometricAuthenticationTechnologies12345:(1):;(2):;(3):;;(4):;(5):21)2)3)1)2)/1-11-1Figure1-1AFrameworkofFaceRecognitionSystem1.2“”“”“”3“”/“”“”11-2Figure1-2AnEmbedSystemofFaceRecognition1.3DNA4MasterCard(PIN)ATMATM3-3,0001.4DM642DM6425242.162.22.2.1----CISCX86RISCARMMIPSPowerPCSPARCSUN(1).(2).DSP(3).(4).(OS)7(5).(6).(7).DSP“”(8).(9).(10).(11).ARMRISC(12).OS82.2.2DSPDSPDSPDSPDSP1PhilipsTrimediaTrimediaPhilips32//I2CPCISDRAMCPUTM1500300MHz2ADDSPADDSPDSPDSPADSP21XXDSPADSP21XXXDSPADDSP24162138EPROMADSPDSPADSP2181ADDSP48403240IEEE32×48Cache3~4ADSP210604211I/OSRAMI/O25nsDSP3TIC64xDM64xC64xTI9CPUTrimediaBSP1GHzC64168000MIPSC64FPGATIDM64xC64xC64TITIDM64x2.2.3DM642TITMS320DM64xDSPDM6421C64x600MHzCPU720MHz3264321.5W216K16K256K310/64(EMIF)64EDMA3I2C32/66MHzPCI10/100MbpsEMAC42.32-1Figure2-1SystemBlockDiagram2-1I2C1TI11DM642DM64232SDRAM8DM6428MFLASHDM6422PhilipsSAA7113DSP3ADIADV7171BT656DM6422.4TIDM642DM6421233.14:2:2800KBDM642DM642FLASHDM642SDRAMFLASHDM6423.1.1DM642(EMIF)DM642C6000DSPEMIFDM642DM642EMIF1SDRAM8163264SDRAM2816326413SRAMROMFLASHFIFO38163264SBSRAMSRAMFIFODM642EMIF3-1EMIFECLKOUTnEMIFEMIFECLKINCPUCPUEA[20:19]CE[3:0]#CPUBE[7:0]#64EMIFSDRAMCE0SDRAMSDCAS#SDRAS#SDWE#EMIF416ED[15:0]C600032EMIFECLKINECLKOUT1ECLKOUT2ED[63:0]EA[22:3]CE[3:0]#BE[7:0]#ARDYSOE3#AOE#/SDRAS#/SOE#ARE#/SDCAS#/SADS#/SRE#AWE#/SDWE#/SWE#HOLD#HOLDA#BUSREQPDT#SDCKE#ControlregistersInternalperipheralbusEnhanceddatamemorycontrollerSharedbyallexternalinterfacesMUXedAsynchronous/SDRAM/synchronousmemorycontrol3-1DM642EMIF[2]Figure3-1DM642EMIFInterfaceSignals[2]143.1.2SDRAMEMIFSDRAMSDRAMSynchronousDynamicRandomAccessSDRAMBankSDRAM4BankBankActivateACTVRASCAStRCDSDRAMSDRAMBankSDRAMSDRAM3-13-1SDRAMCKECS#RAS#CAS#WE#ADDRACTVHLLHHBankREADHLHLHBankWRTHLHLLBank15DCABHLLHLA10=HDEACHLLHLBankA10=LREFRHLLLHXSLFREFRLLLLHXMRSHLLLLHLXSDRAMACTVBankBankDEACDCABBankDEACDCABBankREAD/WRTBankBankBurst/CAStCLDQMDQMSDRAMSDRAMA10A10DCAB/DEACDEACBankDCABBankA10BankBankBankBankBankBankACTVtRPREFRSDRAMSDRAM16HY57V643220CT64ms4096SLFREFRSDRAMCKESDRAMSDRAMtRASCKESDRAMMRSSDRAMBurstBurstCASBurstSDRAMSDRAMEMIFDM642EMIFSDRAMDM642SDRAMMRS0x00320x0022SDRAM4BurstCAS32SDEXTTCLEMIF44DM6424SDRAMEMIFBankDEACEMIF4EMIFLRUEMIFSDRAM17EA232HY57V643220CTSDRAM4Bank81132×4×28×211=64KbEA3-23-2EA(64)EMIFEA15EA14EA13EA12EA11EA10EA9EA8EA7EA6EA5EA4EA3232221201918171615141312112322LLL109876543SDRAMBA12BA11A10A9A8A7A6A5A4A3A2A1A0EA15EA142BankLA10EMIFSDRAMDCABEMIFSDRAMSDRAMSDRAMEMIFSDRAM3.1.4EMIFSDRAMEMIFECLKOUT2ECLKOUTnHOLDHOLDSDRAMECLKOUT1EMIF4CECECECTLCECESECCECTLMTYPECE64SDRAMCE0MTYPE0xD18SDRAMSDRAMCESDRAMSDCTLSDRAMSDTIMSDRAMSDEXTEMIFSDRAMSDRAMSDRAMSDCTLSDBSZSDRSZSDCSZHY57V6432204Bank118SDRAMtRCDACTVREAD/WRTtCL(CAS)EMIF100MHztcyc=10nsHY57V643220PCBtRCD18nsTRCD=tRCD/tcyc-10.812nsRD2WRSDRAMSDRAMCASEMIFEMIFDQMBurstRD2WR3-219RowColAACTVREADQ0ColBWRTD0D1D2D3TRCDTCLREADToWRTHi-ZDQTCL=3DQMCommandAddressCLKTurnaroundcycle3-2SDRAMFigure3-2SDRAMReadAndWriteTimingDiagram(ReadTerminatedByWrite)EMIFPERIODHY57V64322064ms409615.625us15.625us/10ns=0x61BPERIOD0x6001SDRAM3-3SDRAM100MHzDM642SDRAM3-3SDRAMSDRAM0x47225000SDRAM0x00000600SDRAM0x000545093.1.3FLASHEMIFSDRAMFLASH20M29W640DBFLASHE#G#W#3-43-4M29W640DBE#G#W#A0-A21/DQ15-DQ0LLHLHLXHHXHi-ZHXXXHi-ZHLXW#E#G#E#G#E#G#FLASHE#W#G#FLASHREADFLASHREADFLASHM29W640DB10010xff210xffFLASHM29W640DB12764KB88KB127×64K+8×8K=8MBM29W640DB160x05550x00100x0030FLASHFLASHDQ7DQ5DQ7DQ700xffFLASHREADDQ71DQ7FLASHFLASHREADDQ51FLASH3-322STARTSendProgramorErasecommandReadDQ5&DQ7atVALIDADDRESS+DQ7=DATADQ5=1ReadDQ7atVALIDADDRESS+DQ7=DATAFAILPASSYESYESYESNONONOVALIDADDRESSmeansaddressjustprogramedorerased+:3-3FLASH/Figure3-3FLASHProgram/EraseFlowchartFLASHFLASHEMIFEMIFAOE#AWE#ARE#CEFLASHEMIFSetupStrobeHoldEMIFCE#AOE#BE#EAARE#ARE#ARE#EDAOE#CECE#CE