台湾半导体封装工艺

立力IC識IC識IC識(Card)4(Gate)3(Board)01IC•IC來ICIC•離粒•理率便•力IC•切(WaferSawing)•(DieAttaching)•(WireBonding)•(Molding)•切(Trimming/Forming)•(Marking)•(Inspecting)IC•––流––•IC–金–––(Popcorn)–(Void)–(Delaminating)流金金金金流金流C-MOLDGlobal-FlowAnalysisLamb'sEquationLocal-FlowAnalysisδ=+==−=ρπρηNguyen'sFormulaWire-DeformationAnalysisCircularArchFormulaANSYS'sFormula金度Section0Section1Section2Section3Region1Region3Region2Region1Region2Region3Section0Section1Section3Section2:Thecross-sectionwirenumberofthewireregion:Thewirediameter:Thecross-sectionlengthofthewireregion:Thecross-sectionwireheightinthecavity:ThegapthicknessofthecavitynWdWLShWtCthLdnCWSWWSF++=*2**1πCAEIC•–C-MOLDReactiveMolding•流–理•立•料參數參數––理•不–••利數(multiplicityfactor)來金連Connector料•流行–•行–()()21121mmKKααα−+=&⎟⎠⎞⎜⎝⎛−=TEAK111exp⎟⎠⎞⎜⎝⎛−=TEAK222exp()()()()()αααατγηηαγη211*001,,CCgelgelnTTT+−⎥⎥⎦⎤⎢⎢⎣⎡−⎥⎦⎤⎢⎣⎡+=&&()⎟⎠⎞⎜⎝⎛=TTBTbexp0ηCAE力•料–臨金•料–度切率金量•力–Lamb’sModelSDUCPwnD×=22ρ()[]ReReCDln002.28−=π12346891011121314181920E664E665N101N111N106N10851715716Uθar=θurur•力ThermalStressesinanElectronicPackagePotentialRisksites&FailureModesMechanicsIssuesinICpackageDesignandReliabilityFailureAnalysisofBGAFailureanalysiscanbeusedfor;•Identificationofmaterials-relateddefects.•Solvingmanufacturingproblems.•Solvingservice-relatedproblems.•Providingcorrectiveorpreventionmeasures.•Providemanufacturers’insuranceorlegaldefense/claimcases.•Improveproductdesign,enhanceyield&improveproductreliability.RoleofF/A-ProblemIdentification•1.Failureanalysisisnotjusttoconfirmthefailures,itistolocatetherootcauses.•2.Therightattitudeshouldbe:1)Whyitfailed?2)Howitfailed?3)Whatshouldbedonenow?4)Howdoweimprovebetter?FailureAnalysisofFlipChipbyStressTestsKindsofStressTests1)PreconTest(PreconditioningTest)2)T/CTest(TemperatureCyclingTest)3)HTST(HighTemperatureStorageTest)4)T&HTest(Temperature&HumidityTest)5)PCT(PressureCookerTest)FlipChipBGAStructureChipChipBuild-upPWBUnderfill(Epoxy)SolderBumpSolderBall(63Sn/37Pb)PreconditioningTestToknowtheworkabilityofSemiconductordevicesafterenvironmentalstressesandsolderingPCBPCBFlipChipFlipChip•ChecktheworkabilityjustaftersolderingProceduresofPreconTestEXT.VisualINSP&O/STestSAMInspectionTEMPCycleTest(-55’C/125’C,5X)DryBake(125’C,24HRS)Temp&HumidityTest(Level1,2,3,4,5,6)VPSorIRReflow(220deg.C,3X)SimulateTempChangesbytransportSimulateDryingProcessSimulateMoistureAbsorptioninFloorSimulateSolderingProcessElectricalTestNon-DestructiveTestusingSAMDecisionEXT.VisualINSP&O/STestSAMInspectionElectricalTestNDTusingSAMMoistureSensitivityLevelsMoistureSensitivityLevelsLevelT&HCond.(C/%RH)FloorLifeTimeafterUnpack12345685/85,168HRS85/60,168HRS30/60,192HRS30/60,96HRS30/60,72HRS30/60,6HRSUnlimited1Year168HRS(1Week)72HRS(3Days)48HRS(2Days)6HRSScanningAcousticMicroscopeDefectsafterPreconTestDefectsafterPreconTestUnderfillBumpDieSubstrate1.Delamination2.DieCrack3.BumpCrack4.UnderfillCrack5.ElectricalOpen/ShortDefectsafterPreconTestDefectsafterPreconTestDieCrack&DelaminationBumpCrackbyDelaminationDieDieUnderfillUnderfillBumpCrackBumpCrackBumpBumpDieDieUnderfillUnderfillDelaminationDelaminationCrackCrackDefectsafterPreconTestCausesofDefectsafterPreconTestCausesofDefectsafterPreconTest•1.MoistureExistInsideUnderfillMaterialLiquidtoGas:VolumeExpansion1244X•2.FluxResidueonDieSurfaceafterFlipChipattachImprovementSuggestionsImprovementSuggestions•1)UseHighMoistureResistantUnderfill•2)CleanaSurfaceofDieafterFlipChipattach–(removeaFluxresidue)II.ReliabilityTestII.ReliabilityTestToknowtheworkabilityofSemiconductordevicesafterBoardMountinginrealsituationswhichcanbeinducedbyactualusersFlipChipFlipChipPCBPCBRelRel.Test.TestPreconPreconTestTestProcedureofReliabilityTestProcedureofReliabilityTestPRECONTESTT/CHTST&HPCT1.TemperatureCyclingtest1.TemperatureCyclingtestPurposeofT/CtestPurposeofT/CtestToknowthedurabilityofSemiconductorpackageresistingexpansionandshrinkagebyhighandlowtemperature.TemperatureCycleTestTemperatureCycleTest-55CAir125CAirTestConditions1)Temp:+125/-55deg.C2)Time:15min/zone3)Read-outPoint:1000cycleMeasurementOpen/ShortTestEffectsofT/CTestEffectsofT/CTest125CAir-55CAirExpansionShrinkageFailuresafterT/CTestFailuresafterT/CTest1)OpenFailureduetoBumpCrack2)ShortFailureduetoDieCrackUnderfillBumpDieSubstrateBumpCrackafterT/CTestBumpCrackafterT/CTestDieUnderfillBumpBumpCrackBumpCrackbySolderBumpFatigueBumpCrackinsp.usingC-Scan&B-ScanCrackUnderfillPCBUnderfillUnderfillDie2~32~3milmil112233132312DieUnderfillImprovementPlanofT/CFailuresImprovementPlanofT/CFailuresReducetheCTEdifferenceBetweenUnderfill&Die.2.HighTempStorageTest2.HighTempStorageTestPurposeofHTSTPurposeofHTSTToknowthedurabilityofSemiconductorpackagewhenexposedunderthehightemperatureforlongtime.HighTemperatureStorageTestHighTemperatureStorageTest150CN2gasTestConditions1)Temp:150deg.C2)Read-outPoint:1000HRSMeasurementOpen/ShortTest3.Temperature&Humidity(T&H)Test3.Temperature&Humidity(T&H)TestPurposeofT&HtestPurposeofT&HtestToknowthedurabilityofSemiconductorpackageunderthehightempandhumidityconditionTemperature&HumidityTestTemperature&Humid