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SoC0.13IVC1SoC12090SoC(SystemonaChip)3C2PCSoCSoCSoCIPITEMI3,PDASoCDMA4USB5SoCSoC0.1345[2]SoCRTLSoCEDA61InputVectorControl2Computer,CommunicationsandConsumerelectronics3ElectroMagneticInterference4DirectMemoryAccess5UniversalSerialBus6ElectronicDesignAutomation2SoCCMOSCMOSPN12SoC[1]LeakageitShortCircuSwitchingPPPP++=1leakshortVIAVIfACV++=τ22fAVCτ1VinTVinPNVddCLVoutVddVinNPCL∫∫−+=TToutddPToutNSwitchingdtVVtiTdtVtiTP2/2/0))((1)(1∫∫−−+=00)()(ddddVoutddoutddLVoutoutLVVdVVTCdVVTCTVCddL/2=2ddLVfC=301P10N22/VCddLLC22/VCddL3212VinVTnVinVdd|VTp|VTnN,VTpPNPVddGroundddmeanitShortCircuVIP.=TVVtdd12/)(3τβ−=4τβTddVtV4LCLCLCPNPN)1()(tmDStmTGSVVnVVVssubeeWII−−−=tmTVVen−5kT50.13qkTVtm/=qTV3SoCSoCRTLSoC(2)5V3.3V1.8V1.3Vnoisemargin0.13(5)MTCMOS(Multi-ThresholdVTCMOS)VTCMOS(VariableThresholdVTCMOS)nNwellVddpPwell0Nwell2VddPwell1VddSoCSoC15~20%70%[3][4]VswingfAVCVPswings=6VswingDominoChargeRecyclingBus[5]10%SoCCMOSEDACMOSFullAdderCMOS[6]CPL7RTLglitch--Spuriousswitch,hazardsAglitchglitch7ComplementaryPasstransistorLogicglitch16151glitchWallacetreeglitch[7][8]glitchglitchbufferglitchglitchglitch(parallel)[9][10]132232(PIPELINE)n(i-1)i[9][10][10]t(t+1)753SoCHammingHamming[11]HammingGray[12]50%Gray[13]CPU1230%60%“”4SoCEDAAveragePowerPeakPower[10]0.18SoC90%~99%3SwitchingActivity4EDAEDA3[2]ShekharBorkar,CircuitResearch,IntelLabspattern-independentprobabilistictechnique4[10]SoCSynopsysPowerCompiler[14]SoCSAIF810018SpatialArchiveInterchangeFormatSAIFPowerCompilerSAIFSynopsysPrimePower[15]PowerCompilerPrimePowerSAIFVCDValueChangeDumpIEEE1364ASCII[16]5VCDCPUPrimePowerSoC0.13VERILOGSDFSynopsys.dbWireCapPrimePowerVCDVCD+FSDB/5PrimePower5SoC30.181%~3%45SoCsleepCMOS[17]6Artisan0.13NAND4BBX1[18]00111100101100IVC6Smic0.134NANDNAND4BBX11002100NP[19][20]hot-spotsgainfunctiongreedyalgorithms[21]SoCSmic0.1360%0.14%15~40%SoC/SoCSoC6SoCEDAEDASoCEDAEDAIVCEDASoCSoCEDASoC[1]Mudge,T.Power:afirst-classarchitecturaldesignconstraint.Computer,Volume:34,Issue:4,April2001Pages:52–58[2]dragonstar.ict.ac.cn/workshop/ws012.ppt[3]DakeLiu;Svensson,C.PowerconsumptionestimationinCMOSVLSIchips.Solid-StateCircuits,IEEEJournalof,Volume:29,Issue:6,June1994Pages:663–670[4]Rjoub,A.;Koufopavlou,O.;Nikolaidis,S.Low-power/low-swingdominoCMOSlogic.CircuitsandSystems,1998.ISCAS'98.Proceedingsofthe1998IEEEInternationalSymposiumon,Volume:2,31May-3June1998Pages:13-16vol.2[5]Yamauchi,H.;Akamatsu,H.;Fujita,T.Anasymptoticallyzeropowercharge-recyclingbusarchitectureforbattery-operatedultrahighdatarateULSI's.Solid-StateCircuits,IEEEJournalof,Volume:30,Issue:4,April1995Pages:423–431[6]Quintana,J.M.;Avedillo,M.J.;Jimenez,R.;Rodriguez-Villegas,E.Low-powerlogicstylesforfull-addercircuits.Electronics,CircuitsandSystems,2001.ICECS2001.The8thIEEEInternationalConferenceon,Volume:3,2-5Sept.2001Pages:1417-1420vol.3[7]Raghunathan,A.;Dey,S.;Jha,N.K.Registertransferlevelpoweroptimizationwithemphasisonglitchanalysisandreduction.Computer-AidedDesignofIntegratedCircuitsandSystems,IEEETransactionson,Volume:18,Issue:8,Aug.1999Pages:1114–1131[8]Leijten,J.;vanMeerbergen,J.;Jess,J.Analysisandreductionofglitchesinsynchronousnetworks.EuropeanDesignandTestConference,1995.ED&TC1995,Proceedings.,6-9March1995Pages:398-403[9]WolfgangNebel,JeanMermetLowPowerdesignindeepsubmicronelectronics.Norwell,MA,USAKluwerAcademicPublishers1997[10]KaushikRoy,SharatPrasad.LowPowerCMOSVLSICircuitDesign[M].NewYork:AWileyIntersciencePublication,2000.[11]Stan,M.R.;Burleson,W.P.Bus-invertcodingforlow-powerI/O.VeryLargeScaleIntegration(VLSI)Systems,IEEETransactionson,Volume:3,Issue:1,March1995Pages:49–58[12]Hakenes,R.;Manoli,Y.Asegmentedgraycodeforlow-powermicrocontrolleraddressbuses.EUROMICROConference,1999.Proceedings.25th,Volume:1,8-10Sept.1999Pages:240-243vol.1[13]QingWu,M.Pedram,X.Wu,ClockGatingandItsApplicationtoLowPowerDesignofSequentialCircuits,IEEETransactionsonCircuitandSystems,Part1,Vol.47,No.3,pp.415-420,Mar.2000.[14]SynopsysPowerCompilerUserGuideU-2003.06-QA,June2003[15]SynopsysPrimePowerManualReleaseU-2003.06-QA,June2003[16]IEEEStd1364-1995IEEEStandardHardwareDescriptionLanguageBasedontheVerilogHardwareDescriptionLanguage-Description.[17]ZhanpingChen;Johnson,M.;LiqiongWei;Roy,W.;EstimationofstandbyleakagepowerinCMOScircuitconsideringaccuratemodelingoftransistorstacks;LowPowerElectronicsandDesign,1998.Proceedings.1998InternationalSymposiumon,10-12Aug.1998Pages:239–244[18]0.13umstandcelllibraryforASICdesignprovidedbyArtisanComponents,Inc.artix(v4.37.10)-artichar(v3.67.12.B6.1)-syntech(1.58).process(tt).voltage(1.2v).[19]Halter,J.P.;Najm,F.N.;Agate-levelleakagepowerreductionmethodforultra-low-powerCMOScircuits.CustomIntegratedCircuitsConference,1997.,ProceedingsoftheIEEE1997,5-8May1997,Pages:475–478[20]Bobba,S.;Hajj,I.N..MaximumleakagepowerestimationforCMOScircuits.Low-PowerDesign,1999.Proceedings.IEEEAlessandroVoltaMemorialWorkshopon,4-5March1999,Pages:116-124[21]JeffNelson,JoshPieper.FastAlgorithmsforLeakageReductionUsingInputVectorCo