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FPGAX:,,FFTFIR,(FPGA)DSP,FPGA,DSP,,,DSP,DSP,DSPDSPDSP2,DSPDSP,DSP(ASIC)DSP,FPGAFPGA(coarse-grained)(fine-grained)2,,FPGA,Xilinx4000FPGA(CLB-Config2urableLogicBlock)2432,AlteraFLEX10KFPGA(LE-LogicElement)4SRAMFPGAA2SIC,ASICFPGADSPDSP,FPGA,Altera(HDL)DSP,FIRFFTDSPDSP,11FFTFFT,AlteraFFT(DIF-DecimationinFrequency),,,,,AlteraFFT3,,I/O,,FPGARAM,1920001X710077RAM1FFT,AlteraI/O,FFT1AlteraFFTAlteraFFTonchip,,I/O,FPGAFFT21FIRAlteraDSPFIR816243264FIR,28FIR,8FIR3(a)8FIR,(1)2Altera8FIRy(n)=8n=1x(n)h(n)(1)FIR,:h(1)=h(8)h(2)=(h(7)h(3)=h(6)h(4)=4h(5)(2),3(b),4FIR8FIR8,FIRFIR,1,,4FIR31FPGA5,s(k)=2sin5(k+k0)N(3)N,N=16,k0n(k)=2sin2kN(4),x(k)=s(k)+n(k)(5)292000138FIR45n(k)=cos2kN(6)LMS,(7)(8)(9):(k)=x(k)-(w0(k)n(k)+w1(k)n(k-1))(7)w0(k+1)=w0(k)+2(k)n(k)(8)w1(k+1)=w1(k)+2(k)n(K-1)(9)6FPGA,,7256AlteraFLEX10KFPGA,30MSPS,,3920001,6725641ASIC,,,;DSP,ASIC,FPGA,SRAMFPGA,FPGA,,,Xilinx6200CLAFPGA,FPGA150ms(),(RTR-RunTimeReconfiguration),5000FPGA,FPGA4,FP2GAFPGA,11,DSPFPGA,,:4920001,FPGA2N,2N,,,,FFTFIR,;,,,,,,,FPGA,,,8FLEX10K44881616LEEAB,,821,,FPGAFIR,2,,MSPS,,FPGA,2,AlteraFPGA8864FIR,,100MSPS,50%31FPGADSPDSPFPGA,DSP,,FPGADSPXilinx4000RAM,FPGA161bitRAM/ROMAlteraFLEX10KAPEX20KEAB(EmbeddedAr2rayBlock),EAB204811024251242568bitRAM,,,RAMROMFIFORAMAlteraFPGARAMXilinxRAM,EAB,DSP,FLEX10KEAB,,EABXilinxFPGADSP,RAM,RAM,,,5920001RAMFIRFPGA,DSPDSPFPGA,FPGA,DSPFPGA,[1]A.V.OppenheimandR.WSchafer.DigitalSignalProcessing,Prentice-Hall,1975.[2]BernardWidrowandSamuelD.Stearns.AdaptiveSig2nalProcessing,Prentice-Hall,1985.[3]AlteraCorporation.AlteraDigitalLibrary,December1998.[4]JohnVillasenorandBradHutchings.TheFlexibilityofConfigurableComputing,IEEESignalProcessingMaga2zine,Vol.15No.5,September1998.[5]VeselinIvanovc,LjubisaStankovicandDusanPetranovic.FiniteWord-LengthEffectsinImplementa-tionofDistributionsforTime-FrequencySignalAnalysis,IEEETransactionsonSignalProcessing,Vol.46No.7,July1998.1991,,,,,(ASCIET),,,,7030,:----,:(),(JSTAR),T-72,6920001