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论文题目：基于FPGA的数字示波器1.摘要···························································································32.原理···························································································33.系统方案对比及分析······································································43.1.以FPGA来实现整个系统······························································43.2.采用DSP与FPGA来实现整个系统··················································43.3.采用FPGA与单片机来实现整个系统···············································44.系统设计方案···············································································45.系统框图·····················································································56.系统技术指标···············································································67.AD模块简介·················································································68.频率测量模块及方案比较································································68.1.测周期法··················································································68.2.测频率法··················································································78.3.方法选择及使用·········································································78.4.Verilog设计结构·······································································89.数据处理模块···············································································910.FIFO存储模块·············································································910.1.FIFO_1····················································································910.2.FIFO_2····················································································911.NiosII软核模块······································································1012.VGA显示··················································································1013.系统软件构架设计·····································································1113.NiosII软件实现······································································1314.1.DMA传输···············································································1314.2.1.PIO中断··············································································1414.系统的测试和分析······································································1515.总结························································································2216.参考文献··················································································231.摘要随着信息技术的发展，对信号的测量技术要求越来越高，示波器的使用越来越广泛。数字示波器是模拟示波器技术、数字化测量技术、计算机技术的综合产物，他主要以微处理器、数字存储器、A/D转换器和D/A转换器为核心，输入信号首先经A/D转换器转换成数字信号，然后存储在RAM中，需要时再将RAM中的内容读出，经D/A转换器恢复为模拟信号显示在示波器上，或者通过接口与计算机相连对存储的信号作进一步处理，这样可大大改进显示特性，增强功能，便于控制和智能化。这种数字示波器中看到的波形是由采集到的数据经过重构后得到的波形，而不是加到输入端上信号的波形。设计提出一个经过优化的数据采集方法，辅以FPGA为主控制器和必备的外围电路完成了基于FPGA的数字存储示波器的设计。系统最大限度地利用了FPGA的高速数字信号处理能力以及众多硬核和软核内嵌的特性，降低了成本和开发难度，且性能优良。2.原理数字示波器具有存储数据的能力，数字存储就是在示波器中以数字编码的形式来贮存信号。当信号进入数字存储示波器，或称DSO以后，在信号到达CRT的偏转电路之前，示波器将按一定的时间间隔对信号电压进行采样。然后用一个模/数变换器（ADC）对这些采样值进行变换从而生成代表每一个采样电压的二进制字。这个过程称为数字化。获得的二进制数值贮存在存储器中，对输入信号进行采样的速率称为采样速率。采样速率由采样时钟控制。对于一般使用情况来说，采样速率的范围从每秒20兆次（20MS/s）到200MS/s。存储器中贮存的数据用来在示波器的屏幕上重建信号波形。所以，在DSO中的输入信号接头和示波器CRT之间的电路不只是仅有模拟电路。输入信号的波形在CRT上获得显示之前先要存贮到存储器中，我们在示波器屏幕上看到的波形总是由所采集到数据重建的波形，而不是输入连接端上所加信号的直接波形显示。示波器原理框图如下：3.系统方案对比及分析3.1.以FPGA来实现整个系统以可编程器件FPGA为主控来实现整个系统，设计时电路相对简洁，因为FPGA的可编程性适用于模块化设计，内部集成大量电路模块，如A/D转换器，锁相环，甚至有些FPGA内部嵌入ARM相关处理器，DSP模块，电源模块，所以FPGA可以实现DSP相关算法，可以做大量运算，并且它的处理速度由于其并行性，在协调多个模块的工作时候非常方便，控制能力强。在整个数值示波器的设置中，通过采样数据然后存储，再做相应的数据处理，执行相关任务，完全可以实现示波器的基本功能，设计可行性非常高。辅助一些外围电路模块，基本能实现设计期望达到的功能和参数。3.2.采用DSP与FPGA来实现整个系统采用DSP和FPGA开发起来比较灵活，升级也容易，通用性强，在以FPGA为主控的同时辅以DSP作为信号处理，提高系统的效率。但是DSP在与外围电路接口的时候，比如说LCD显示和键盘进行通信时候，因为DSP速度非常快，而LCD显示器和键盘电路比较慢，会造成资源浪费。3.3.采用FPGA与单片机来实现整个系统采用FPGA与单片机来实现，主要是利用单片机进行一些外部接口的监控，对键盘电路和显示电路实时更新，减轻FPGA主控的任务。且单片机控制比较简单，现在大多单片机内设比较丰富，能很好地胜任工作。但是这里使用单片机进行控制，增加了一些额外开销，且单片机任务比较简单，而且不多，本身FPGA集成一些内核可以进行比普通单片机更快的处理，再另外使用单片机有点多余。综上，直接采用FPGA为主控芯片，资源足够丰富，就能很好地满足设计需求，不需要再多的控制器，因此直接选用方案一。4.系统设计方案当信号进入数字存储示波器时，首先对信号进行前置处理，然后将按一定的时间间隔对信号电压进行采样，之后对这些采样值进行数字化，即通过AD转换器变换得到代表每一个实际电压的二进制数字，进一步把这些数字贮存在存储器中，最终根据数字大小按一定比例把每一个采样点重现在显示器上，这样就能看到清晰的波形。整个系统由高速采样电路、FIFO存储器、时钟分时电路、控制器FPGA和显示电路构成。数字示波器系统框图如图所示,其中FPGA构成控制器,信号从探头输入,一路送入高速AD转换器对信号进行采样,采样所得的数据通过处理后存入FIFO存储器中，FIFO模块有两个，前者FIFO1通过开关来控制数据采样频率，后者FIFO2通过脉冲来控制其工作状态；当FIFO2存满后通知NiosII软核处理器,NiosII从FIFO存储器中通过DMA形式接受数据进行处理,然后将波形和频率等数据通过VGA显示在显示器上。时钟电路为高速AD转换器和FIFO存储器提供不同的频率信号,作为不同水平扫描时的采样时钟频率。输入信号第二路送入FPGA板的一个串口，通过频率计算模块计算该信号的频率。FPGA以被测信号的频率数据作为频率、水平扫描、灵敏度和峰峰值计算、显示的依据。5.系统框图整个系统框图大概如上图所示，通过FPGA硬件设计和软件设计相结合，以NIOS为主控，配合上外部硬件设计，实现功能。首先数据经过AD转换后变成14位数据，直接进入数据处理模块，数据会进行相应的伸缩变化，并且转换为16位数据。处理后的数据进入FIFO，这块FIFO用来做一级缓冲，一直在采样，采样满会直接溢出，就是说FIFO一直都会存在数据，接着数据会传到第二块FIFO，这块FIFO有一个触发电路控制，控制进行数据采样。这里的FIFO是nios的外设，已经挂载到总线，传入的数据会在DMA通道的作用下直接传输到内部的ram，再由nios控制显示输出。其中频率测量模块或者峰值模块均有NIOS内核监控，并实时显示。6.系统技术指标a)带宽：4MHz（根据五倍准则，示波器的误差不会超过±2％）b)测量频率范围：0～4MHzc)电压检测：0-2Vp-pd)水平灵敏度：e)垂直灵敏度：0.05v/div、0.15v/div、1v/divf)AD采样率：65MHzg)存储深度：512h)通道：双通道7.AD模块简介高速A/D采集经过模拟信号调理电路后的信号，采样值送入FPGA内缓存，经过相应数据处理后，ARM把数据取走。设计采用terasic公司的