EDA数字秒表课程设计

程序：(1)时基分频模块的VHDL源程序（CB10.VHD)LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCB10ISPORT(CLK:INSTD_LOGIC;——输入时钟信号CO:OUTSTD_LOGIC);——分频输出信号ENDCB10;——实体描述ARCHITECTUREARTOFCB10IS——结构体描述SIGNALCOUNT:STD_LOGIC_VECTOR(3DOWNTO0);——硬件系统的基本数据对象BEGINPROCESS(CLK)——进程敏感信号BEGINIFRISING_EDGE(CLK)THENIFCOUNT=1001THENCOUNT=0000;CO='1';ELSECOUNT=COUNT+1;CO='0';ENDIF;ENDIF;ENDPROCESS;ENDART;(2)控制模块的VHDL源程序（CTRL.VHD)LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCTRLISPORT(CLR,CLK,SP:INSTD_LOGIC;EN:OUTSTD_LOGIC);——CLR：清零信号CLK：脉冲输入端SP：计数输入端EN：输出端END;ARCHITECTUREBEHAVEOFCTRLISCONSTANTS0:STD_LOGIC_VECTOR(1DOWNTO0):=00;CONSTANTS1:STD_LOGIC_VECTOR(1DOWNTO0):=01;CONSTANTS2:STD_LOGIC_VECTOR(1DOWNTO0):=10;CONSTANTS3:STD_LOGIC_VECTOR(1DOWNTO0):=11;TYPESTATESIS(S0,S1,S2,S3);——表达四个状态的位矢量SIGNALCURRENT_STATE,NEXT_STATE:STATES;BEGINCOM:PROCESS(SP,CURRENT_STATE)——决定转换状态的进程BEGINCASECURRENT_STATEISWHENS0=EN='0';——选中状态为S0、EN='0'IFSP='1'THENNEXT_STATE=S1;ELSENEXT_STATE=S0;ENDIF;WHENS1=EN='1';——选中状态为S1、EN='1'IFSP='1'THENNEXT_STATE=S1;ELSENEXT_STATE=S2;ENDIF;WHENS2=EN='1';——选中状态为S2、EN='1'IFSP='1'THENNEXT_STATE=S3;ELSENEXT_STATE=S2;ENDIF;WHENS3=EN='0';——选中状态为S3、EN='0'IFSP='1'THENNEXT_STATE=S3;ELSENEXT_STATE=S0;ENDIF;ENDCASE;ENDPROCESS;SYNCH:PROCESS(CLK)——时序进程BEGINIFCLR='1'THENCURRENT_STATE=S0;ELSIFCLK'EVENTANDCLK='1'THENCURRENT_STATE=NEXT_STATE;ENDIF;ENDPROCESS;ENDBEHAVE;（3）计时模块的VHDL源程序①十进制计数器的VHDL源程序——cdu10.vhdLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYcdu10ISPORT(CLK:INSTD_LOGIC;——时钟信号CLR:INSTD_LOGIC;——清零信号EN:INSTD_LOGIC;——计数使能信号CN:OUTSTD_LOGIC;——计数输出信号COUNT10:OUTSTD_LOGIC_VECTOR(3DOWNTO0));——计数值ENDcdu10;ARCHITECTUREARTOFcdu10ISSIGNALSCOUNT10:STD_LOGIC_VECTOR(3DOWNTO0);BEGINCOUNT10=SCOUNT10;PROCESS(CLK,CLR,EN)BEGINIF(CLR='1')THENSCOUNT10=0000;CN='0';ELSIFRISING_EDGE(CLK)THEN——脉冲为上跳沿触发IF(EN='1')THENIFSCOUNT10=1001THENCN='1';SCOUNT10=0000;ELSECN='0';SCOUNT10=SCOUNT10+'1';ENDIF;ENDIF;ENDIF;ENDPROCESS;ENDART;②六进制计数器的VHDL源程序——cdu6.vhdLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYcdu6ISPORT(CLK:INSTD_LOGIC;CLR:INSTD_LOGIC;EN:INSTD_LOGIC;CN:OUTSTD_LOGIC;——计数输出信号COUNT6:OUTSTD_LOGIC_VECTOR(3DOWNTO0));——计数值ENDcdu6;ARCHITECTUREARTOFcdu6ISSIGNALSCOUNT6:STD_LOGIC_VECTOR(3DOWNTO0);BEGINCOUNT6=SCOUNT6;PROCESS(CLK,CLR,EN)BEGINIF(CLR='1')THENSCOUNT6=0000;CN='0';ELSIFRISING_EDGE(CLK)THENIF(EN='1')THENIFSCOUNT6=0101THENCN='1';SCOUNT6=0000;ELSECN='0';SCOUNT6=SCOUNT6+'1';ENDIF;ENDIF;ENDIF;ENDPROCESS;ENDART;③计时器的VHDL源程序——count.vhdLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcountISPORT(CLK:INSTD_LOGIC;CLR:INSTD_LOGIC;EN:INSTD_LOGIC;S_1MS:OUTSTD_LOGIC_VECTOR(3DOWNTO0);——毫秒计数值S_10MS:OUTSTD_LOGIC_VECTOR(3DOWNTO0);——十毫秒计数值S_100MS:OUTSTD_LOGIC_VECTOR(3DOWNTO0);——百毫秒计数值S_1S:OUTSTD_LOGIC_VECTOR(3DOWNTO0);——秒计数值S_10S:OUTSTD_LOGIC_VECTOR(3DOWNTO0);——十秒计数值M_1MIN:OUTSTD_LOGIC_VECTOR(3DOWNTO0);——分计数值M_10MIN:OUTSTD_LOGIC_VECTOR(3DOWNTO0);——十分计数值HOUR:OUTSTD_LOGIC_VECTOR(3DOWNTO0));——小时计数值ENDcount;ARCHITECTUREARTOFcountISCOMPONENTcdu10——元件例化PORT(CLK:INSTD_LOGIC;CLR:INSTD_LOGIC;EN:INSTD_LOGIC;CN:OUTSTD_LOGIC;COUNT10:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDCOMPONENTcdu10;COMPONENTcdu6——元件例化PORT(CLK:INSTD_LOGIC;CLR:INSTD_LOGIC;EN:INSTD_LOGIC;CN:OUTSTD_LOGIC;COUNT6:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDCOMPONENTcdu6;SIGNALA,B,C,D,E,F,G,H:STD_LOGIC;BEGINU1:cdu10PORTMAP(CLK,CLR,EN,A,S_1MS);U2:cdu10PORTMAP(A,CLR,EN,B,S_10MS);U3:cdu10PORTMAP(B,CLR,EN,C,S_100MS);U4:cdu10PORTMAP(C,CLR,EN,D,S_1S);U5:cdu6PORTMAP(D,CLR,EN,E,S_10S);U6:cdu10PORTMAP(E,CLR,EN,F,M_1MIN);U7:cdu6PORTMAP(F,CLR,EN,G,M_10MIN);U8:cdu10PORTMAP(G,CLR,EN,H,HOUR);ENDART;（4）显示模块的VHDL源程序①数据选择器的VHDL源程序（MULX.VHD)LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYMULXISPORT(CLK,CLR,EN:INSTD_LOGIC;S_1MS:INSTD_LOGIC_VECTOR(3DOWNTO0);——毫秒计数器S_10MS:INSTD_LOGIC_VECTOR(3DOWNTO0);——十毫秒计数器S_100MS:INSTD_LOGIC_VECTOR(3DOWNTO0);——百毫秒计数器S_1S:INSTD_LOGIC_VECTOR(3DOWNTO0);——秒计数器S_10S:INSTD_LOGIC_VECTOR(3DOWNTO0);——十秒计数器M_1MIN:INSTD_LOGIC_VECTOR(3DOWNTO0);——分计数器M_10MIN:INSTD_LOGIC_VECTOR(3DOWNTO0);——十分计数器HOUR:INSTD_LOGIC_VECTOR(3DOWNTO0);——小时计数器OUTBCD:OUTSTD_LOGIC_VECTOR(3DOWNTO0);——BCD码输出SEG:OUTSTD_LOGIC_VECTOR(7DOWNTO0));——七段译码输出ENDMULX;ARCHITECTUREARTOFMULXISSIGNALCOUNT:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(CLK)BEGINIFCLR='1'THENCOUNT=1111;ELSIFRISING_EDGE(CLK)THENIFEN='1'THENIFCOUNT=1001THENCOUNT=0000;ELSECOUNT=COUNT+1;ENDIF;ENDIF;ENDIF;ENDPROCESS;PROCESS(CLK)BEGINIFCLK'EVENTANDCLK='1'THEN——时钟上升沿触发输出各位数据CASECOUNTISWHEN0000=OUTBCD=S_1MS;SEG=11111110;WHEN0001=OUTBCD=S_10MS;SEG=11111101;WHEN0010=OUTBCD=S_100MS;SEG=11111011;WHEN0011=OUTBCD=S_1S;SEG=11110111;WHEN0100=OUTBCD=S_10S;SEG=11101111;WHEN0101=OUTBCD=M_1MIN;SEG=11011111;WHEN0110=OUTBCD=M_10MIN;SEG=10111111;WHEN0111=OUTBCD=HOUR;SEG=01111111;WHEN1000=OUTBCD=S_1MS;SEG=11111110;WHEN1001=OUTBCD=S_10MS;SEG=11111101;WHENOTHERS=OUTBCD=0000;SEG=00000000;ENDCASE;ENDIF;ENDPROCESS;ENDART;②BCD七段译码