modelsim使用 + VHDL + testbench + textio

ModelSimHDLVHDLVerilogIEEEModelSimModelSimXEModelSimSEModelSim5.8VHDL2002Verilog2001LinuxHPSUNVHDLVerilogSystemCWindowsSystemCModelSim5.7ModelSimModelSim://=DISK_SERIAL_NUM=c61e85ack=244FEATURExe-starterFEATUREmodeltech2004.121-jan-00permanent000uncounted9C0FA6415C9327086559FlexlmHOSTID=DISK_SERIAL_NUM=c61e85ac61e85aModelSimEDALicenseEDAPADSActiveHDLLicenseServerFLEXlmLicenseManagerModelSimlicenseModelSimLicenseWizardWin95/98autoexec.bat:SETLM_LICENSE_FILE=c:\flexlm\license.datEDAlicense:SETLM_LICENSE_FILE=c:\flexlm\license1.dat;d:\altera\license2.datWin2000NT,LM_LICENSE_FILElicenseFlexlmEDAFlexlmModelSimPELESEPE32WINDOWS98/NT/ME/2000/XPLE32LINUXSE32AIX,HP-UX,LINUX+SOLARIS,WINDOWS98/NT/ME/2000/XP64AIX,LINUX(ITANIUM-2),HP-UX,SOLARISHP-UX,LINUX8.2ModelSimXEII5.7cModelSim--ModelSimXEII5.7c-ModelSim8-2-1WorkspaceTranscriptModelSim8.2.1WindowsAltSpaceBarWindows8.2.2:FileEditViewCompileSimulateToolsWindowHelp1.FileModelSimNewOpenCloseImportSaveDeleteChangeDirectoryTranscriptAddtoProjectRecentDirectoriesRecenProjectsQuit1File/NewFile/NewFloderSourceVHDLVerilogOtherProjectProjectNameProjectLocationDefaultLibraryNameLibraryCreataNewlibraryandalogicalmappingtoitAmaptoanexistinglibraryLirarynameLibraryphycialname2OpenFileProjectDatasetWLF3CloseProjectDataset4ImportModelSimmodelsim.iniModelSim5Save6Delete.mpfmpfModelSim7ChangeDirectoryModelSimISEISEModelSim8TranscriptSaveTranscriptSaveTranscriptAsClearTranscript9AddtoProjectFileSimulationConfigurationFolder10RecentDirectories11RecenProjects12QuitModelSim.2.EditWindows1Copy2Paste3SelectAll4UnselectAll5Find3.ViewWindows1AllWindowsModelSimModelSim2DataflowDataflow3List4Process5Signals6Source7Structure8Variables9Wave10DatasetsDatasetDatasetWorkspaceStructure11Coverage12ActiveProcesses13workspace14Encoding15Properties4.Compile1CompileHDL2CompileOptionsVHDLVerilog3CompileAll4CompileSelect5CompileOrderVHDLVerilog6CompileReport7CompileSummary5.SimulateVC1Simulate2SimulationOptions3RunRun***ns:SimulationOptionsRun-AllContinueRun-NextStepStep-OverRestrat4Break5EndSimulation6.Tool1WaveformCompare2Coverage1003Breakpoints4ExecuteMacro5OptionsTranscriptFile:CommandHistory:SaveFile:SavedLines:LinePrefix:UpdateRate:ModelSimPrompt:ModelSimVSIMPrompt:VSIMPausedPrompt:PausedHTMLViewer:6EditPreferences7SavePreferences7.Window1InitialLayout2Cascade3TileHorizontally4TileVertically5LayoutStyleDefaultInitialLayoutClassic5.5CascadeCascadeHorizontallyTileHorizontallyVerticallyTileVertically6IconChildren7IconAll8DeiconAll8.Help1AboutModelSimModelSim2ReleaseNotesModelSim3WelocmeMenu4PDFDocumentationModelSimPDFSEHTMLDocumentationModelSim5TclHelpTclTclToolsCommandLanguage,C.6TclManPagesTcl7Technotes8.2.3ModelSim8-2-2ModelSim8.2.4ModelSim8-2-3ProjectNow8.3ModelSimModelSimModelSimModelSim1Hz248ISE8.3.11ModelSim--ModelSimXEII5.7c-ModelSim8-3-1ModelSim8-3-1ModelSim2File-New-Project8-3-2ProjectNameDivClkSimuProjectLocationD:/yuProj/modelsim/DivClkModelSimProjectLocationDefaultLibraryNameWorkspaceLibraryworkOK8.3.238-3-38-3-348-3-4CreateNewFileAddExistingFileCreateSimulationCreateNewFolderCreateNewFile8-3-458-3-5FileNameDivClkHDLAddfileastypeVHDLVerilogTCLtextVHDLFolderTopLevelOKAdditemstotheProjectClose8-3-56WorkspaceProjectDivClkHDL.vhdedit-DivClkHDL.vhdlibraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entitydivclk1isPort(clk:instd_logic;divclk:outstd_logic);enddivclk1;architectureBehavioralofdivclk1issignalcounter:std_logic_vector(4downto0):=00000;signaltempdivclk:std_logic:='0';beginprocess(clk)beginifclk'eventandclk='1'thenif(counter=11000)thencounter=00000;tempdivclk=nottempdivclk;elsecounter=counter+'1';endif;endif;endprocess;divclk=tempdivclk;endBehavioral;7File-SaveFile-Close8WorkSpaceDivClkHDL.vhdCompile-CompileAll8-3-68-3-69CompileofDivClkHDL.vhdwassuccessful.10Simulate-Simulate8-3-7DesignworkbehavioralSimulatework.divclk1(behavioral)ResolutionOK8-3-711View-Wave12WaveView-Signals8-3-8Add-Wave-SignalsinDesign13forceclk00,110000-r20000forceclkclk00011000010ns1-r2000020nsrepeat50MHz20ns14countercounterRadix-Decimal15run3us3CPU100168-3-91101us8-3-917Simulate-EndSimulation1850MHz20ns1MHz1usif(counter=11000)thenTnsXns((X/T)/2)-120ns1000ns1us((X/T)/2)-1=((1000/20)/2-1)=24=(1