vhdl加法计数器

6、编写一个4位加法计数器VHDL源程序，要求：复位信号reset低电平清零，变高后在clk上升沿开始工作，输入时钟信号为clk，输出为q。(以十二进制为例)LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcounterISPORT(clk,reset:INSTD_LOGIC;q:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDENTITYpriorityencoderARCHITECTURErtlOFcounterISSIGNALcount:STD_LOGIC_VECTOR(3DOWNTO0);BEGINq=cout;PROCESS(clk,reset)ISBEGINIF(reset=’0’)THENcout=0000;ELSIF(clk’EVENTANDclk=’1’)THENIF(cout=1011)THENcout=0000ELSEcout=cout+’1’;ENDIF;ENDIF;ENDPROCESS;ENDARCHITECTURErtl;4位二进制并行加法器的源程序ADDER4B.VHDLIBRARYIEEE；USEIEEE.STD_LOGIC_1164.ALL；USEIEEE.STD_LOGIC_UNSIGNED.ALL；ENTITYADDER4BIS--4位二进制并行加法器PORT(CIN：INSTD_LOGIC；--低位进位A：INSTD_LOGIC_VECTOR(3DOWNTO0)；--4位加数B：INSTD_LOGIC_VECTOR(3DOWNTO0)；--4位被加数S：OUTSTD_LOGIC_VECTOR(3DOWNTO0)；--4位和CONT：OUTSTD_LOGIC)；ENDADDER4B；ARCHITECTUREARTOFADDER4BISSIGNALSINT：STD_LOGIC_VECTOR(4DOWNTO0)；SIGNALAA，BB：STD_LOGIC_VECTOR(4DOWNTO0)；BEGINAA='0'&A；--将4位加数矢量扩为5位，为进位提供空间BB='0'&B；--将4位被加数矢量扩为5位，为进位提供空间SINT=AA+BB+CIN；S=SINT(3DOWNTO0)；CONT=SINT(4)；ENDART；8位二进制加法器的源程序ADDER8B.VHDLIBRARYIEEE；USEIEEE_STD.LOGIC_1164.ALL；USEIEEE_STD.LOGIC_UNSIGNED.ALL：ENTITYADDER8BIS--由4位二进制并行加法器级联而成的8位二进制加法器PORT(CIN：INSTD_LOGIC；A：INSTD_LOGIC_VECTOR(7DOWNTO0)；B：INSTD_LOGIC_VECTOR(7DOWNTO0)；S：OUTSTD_LOGIC_VECTOR(7DOWNTO0)；COUT：OUTSTD_LOGIC)；ENDADDER8B；ARCHICTUREARTOFADDER8BISCOMPONENETADDER4B--对要调用的元件ADDER4B的界面端口进行定义PORT(CIN：INSTD_LOGIC；A：INSTD_LOGIC_VECTOR(3DOWNTO0)；B：INSTD_LOGIC_VECTOR(3DOWNTO0)；S：OUTSTD_LOGIC_VECTOR(3DOWNTO0)；CONT：OUTSTD_LOGIC)；ENDCOMPONENT；SIGNALCARRY_OUT：STD_LOGIC；--4位加法器的进位标志BEGINU1：ADDER4B--例化(安装)一个4位二进制加法器U1PORTMAP(CIN=CIN，A=A(3DOWNTO0)，B=B(3DOWNTO0)，S=S(3DOWNTO0)，COUT=CARRY_OUT)；U2：ADDER4B--例化(安装)一个4位二进制加法器U2PORTMAP(CIN=CARRY_OUT，A=A(7DOWNTO4)，B=B(7DOWNTO4)，S=S(7DOWNTO4)；CONT=CONT)；ENDART；六进制计数器的源程序CNT6.VHD(十进制计数器的源程序CNT10.VHD与此类似)LIBRARYIEEE；USEIEEE.STD_LOGIC_1164.ALL；USEIEEE.STD_LOGIC_UNSIGNED.ALL；ENTITYCNT6ISPORT(CLK：INSTD_LOGIC；CLR：INSTD_LOGIC；ENA：INSTD_LOGIC；CQ：OUTSTD_LOGIC_VECTOR(3DOWNTO0)；CARRY_OUT：OUTSTD_LOGIC)；ENDCNT6；ARCHITECTUREARTOFCNT6ISSIGNALCQI：STD_LOGIC_VECTOR(3DOWNTO0)；BEGINPROCESS(CLK，CLR，ENA)BEGINIFCLR='1'THENCQI=0000；ELSIFCLK'EVENTANDCLK='1'THENIFENA='1'THENIFCQI=“0101”THENCQI=“0000”；ELSECQI=CQI+'1'；ENDIF；ENDIF；ENDIF；ENDPROCESS；PROCESS(CQI)BEGINIFCQI=“0000”THENCARRY_OUT='1'；ELSECARRY_OUT='0'；ENDIF；ENDPROCESS；CQ=CQI；ENDART；十进制计数器LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;ENTITYcount10ISPORT(clk:INSTD_LOGIC;seg:OUTSTD_LOGIC_VECTOR(6DOWNTO0));ENDcount10;ARCHITECTUREa1OFcount10ISsignalsec:STD_LOGIC;signalq:STD_LOGIC_VECTOR(21DOWNTO0);signalnum:STD_LOGIC_VECTOR(3DOWNTO0);BEGINprocess(clk)----get1hzclockpulsebeginifclk'eventandclk='1'thenq=q+1;endif;sec=q(21);--get1hzclockpulseendprocess;timing:process(sec)beginifsec'eventandsec='1'thenifnum9thennum=num+1;elsenum=0000;endif;endif;endprocess;B1:block--bcd-7segsBegin--gfedcbaseg=0111111whennum=0else0000110whennum=1else1011011whennum=2else1001111whennum=3else1100110whennum=4else1101101whennum=5else1111101whennum=6else0000111whennum=7else1111111whennum=8else1101111whennum=9else0000000;endblock;ENDa1;四位全加器libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityaddisport(a,b:instd_logic_vector(3downto0);cin:instd_logic;s:outstd_logic_vector(3downto0);cout:outstd_logic);endadd;architecturebehofaddisbeginprocess(a,b,cin)ariablex:std_logic_vector(3downto0);variablem,n,l:integer;beginm:=conv_integer(a);n:=conv_integer(b);l:=m+n+conv_integer(cin);x:=conv_std_logic_vector(l,4);s=x(3downto0);cout=x(3);endprocess;endbeh;10位计数器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT10ISPORT(CLK,clr:INSTD_LOGIC;CQ:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDENTITYCNT10;ARCHITECTUREONEOFCNT10ISBEGINPROCESS(CLK,clr)VARIABLELCQ:STD_LOGIC_VECTOR(3DOWNTO0);BEGINIFRST=‘1’THENLCQ:=“0000”;ELSIFCLK’EVENTANDCLK=‘1’THENIFLCQ9THENLCQ:=LCQ+1;ELSELCQ:=“0000”;ENDIF;ENDIF;CQ=LCQ;ENDPROCESS;ENDARCHITECTUREONE;八位串行二进制全加器useieee.std_logic_1164.all;entityproduct_adder_subtracterisport(a,b:instd_logic_vector(7downto0);s:outstd_logic_vector(8downto0));end;architecturebehavioralofproduct_adder_subtracterisbeginbehavior:process(a,b)isvariablecarry_in:std_logic;variablecarry_out:std_logic;variableop2:std_logic_vector(b'range);beginop2:=b;endif;forindexin0to7loopcarry_in:=carry_out;s(index)=a(index)xorop2(index)xorcarry_in;carry_out:=(a(index)andop2(index))or(carry_inand(a(index)xorop2(index)));endloop;s(8)=a(7)xorop2(7)xorcarry_out;endprocess;end;8、根据已给出全加器VHDL程序，试写出一个四位逐位进位加法器的VHDL源程序。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYadder_4ISPORT(A,B:INSTD_LOGIC_VECTOR(3DOWNTO0);Ci:INSTD_LOGIC;Co:OUTSTD_LOGIC;S:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDENTITYadder_4;ARCHITECTURErtlOFadder_4ISCOMPONENTadder_1ISPORT(aa,bb,cci:INSTD_LOGIC;ss,cco:OUTSTD_LOGIC);ENDCOMPONENT;SIGNALC0,C1,C2:STD_LOGIC;BEGINadd1:adder_1PORTMAP(A(0),B(0),Ci,S(0),C0);add2:adder_1PORTMAP(A(1),B(1),C0,S(1),C1);add3:adder_1PORTMAP(A(2),B(2),C1,S(2),C2);add4:adder_1PORTMAP(A(3),B(3),C2,S(0),Co);E