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LIBRARYieee;USEieee.std_logic_1164.ALL;ENTITYshiyan2ISPORT(a0,a1,a2,a3:INstd_logic;y:OUTstd_logic_vector(7DOWNTO0));ENDshiyan2;ARCHITECTUREm1OFshiyan2ISSIGNALa:std_logic_vector(3DOWNTO0);BEGINa=a3&a2&a1&a0;--将端口a3、a2、a1、a0依序连接起来赋给信号aWITHaSELECTy=01110001WHEN1111,01111001WHEN1110,01011110WHEN1101,00111001WHEN1100,01111100WHEN1011,01110111WHEN1010,01101111WHEN1001,01111111WHEN1000,00000111WHEN0111,01111101WHEN0110,01101101WHEN0101,01100110WHEN0100,01001111WHEN0011,01011011WHEN0010,00000110WHEN0001,00111111WHEN0000,01111110WHENOTHERS;ENDm1;

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