PARWAN-CPU-状态机设计

基于FPGA的数字系统设计大作业学号：13091378姓名：邢武天班级：130914题目一：设计Parwan的controlsection内部状态机s1\s2\..\s9\,并给出功能仿真？题目二：利用分层结构设计ParwanCPU,并给出功能仿真?（利用在实验课中所给出的TESTBENCH）实验原理图ControlSectionStructure：s1…s9（如下图所示）InputsandoutputsofPARWANcontrolsections:–Appliedto,categories,signalname,functions实验过程1.1创建工程（1）打开ISE13.x软件，选择File-NewProject在弹出的对话框中输入工程名和路径。（2）单击下一步选择所使用的芯片。Spartan3E开发板的芯片型号为Spartan3EXC3S500E芯片，FG320封装。（3）单击Next，进入工程信息页面，确认无误后，点击Finish完成工程的创建。1.2测试文件(1)选择菜单栏中的Project-NewSource。(2)在SelectSourceType窗口中，选择左侧的VHDLTestBench,在右侧FileName栏中输入文件名par_control_unit_tb(3)单击Next按钮，选择关联文件。1.3实验截图实验代码在实现过程中，除了定义CPU的信号接口外，还设置了一个输出类型的接口，名字叫present_state_value,主要是用来在调试或仿真的过程中输出CPU所处的状态，便于调试分析。整个状态机的实现过程主要使用了case…IS…when逻辑结构。用了present_state和next_state两个状态变量。详细的实现代码如下所示：LIBRARYIEEE;USEIEEE.std_logic_1164.ALL;USEwork.synthesis_utilities.ALL;--ENTITYpar_control_unitISPORT(clk:INstd_logic;--registercontrolsignals:load_ac,zero_ac,load_ir,increment_pc,load_page_pc,load_offset_pc,reset_pc,load_page_mar,load_offset_mar,load_sr,cm_carry_sr,--busconnectioncontrolsignals:pc_on_mar_page_bus,ir_on_mar_page_bus,pc_on_mar_offset_bus,dbus_on_mar_offset_bus,pc_offset_on_dbus,obus_on_dbus,databus_on_dbus,mar_on_adbus,dbus_on_databus,--logicunitfunctioncontroloutputs:arith_shift_left,arith_shift_right:OUTstd_logic;alu_and,alu_not,alu_a,alu_add,alu_b,alu_sub:outstd_logic;--inputsfromthedatasection:ir_lines:INstd_logic_vector(7DOWNTO0);status:INstd_logic_vector(3DOWNTO0);--memorycontrolandotherexternalsignals:read_mem,write_mem:OUTstd_logic;interrupt:INstd_logic;--testpresent_state_value:outstd_logic_vector(3DOWNTO0));ENDpar_control_unit;--ARCHITECTUREdataflow_synthesizableOFpar_control_unitISTYPEcpu_statesIS(s1,s2,s3,s4,s5,s6,s7,s8,s9);SIGNALpresent_state,next_state:cpu_states;SIGNALnext_state_value:std_logic_vector(3DOWNTO0);BEGINclocking:PROCESS(clk,interrupt)BEGINIF(interrupt='1')THENpresent_state=s1;present_state_value=0001;ELSIFclk'EVENTANDclk='0'THENpresent_state=next_state;present_state_value=next_state_value;ENDIF;ENDPROCESSclocking;--sequencing:PROCESS(present_state,ir_lines,status,interrupt)BEGINload_ac='0';zero_ac='0';load_ir='0';increment_pc='0';load_page_pc='0';load_offset_pc='0';reset_pc='0';load_page_mar='0';load_offset_mar='0';load_sr='0';cm_carry_sr='0';--busconnectioncontrolsignals:pc_on_mar_page_bus='0';ir_on_mar_page_bus='0';pc_on_mar_offset_bus='0';dbus_on_mar_offset_bus='0';pc_offset_on_dbus='0';obus_on_dbus='0';databus_on_dbus='0';mar_on_adbus='0';dbus_on_databus='0';--logicunitfunctioncontroloutputs:arith_shift_left='0';arith_shift_right='0';alu_and='0';alu_not='0';alu_a='0';alu_add='0';alu_b='0';alu_sub='0';--memorycontrolandotherexternalsignals:read_mem='0';write_mem='0';CASEpresent_stateISWHENs1=-------------------------------------------1IF(interrupt='1')THENreset_pc='1';next_state=s1;next_state_value=0001;ELSEpc_on_mar_page_bus='1';pc_on_mar_offset_bus='1';load_page_mar='1';load_offset_mar='1';next_state=s2;next_state_value=0010;ENDIF;WHENs2=---------------------------------------2--readmemoryintoirmar_on_adbus='1';read_mem='1';databus_on_dbus='1';alu_a='1';load_ir='1';increment_pc='1';next_state=s3;next_state_value=0011;WHENs3=--------------------------------------3pc_on_mar_page_bus='1';pc_on_mar_offset_bus='1';load_page_mar='1';load_offset_mar='1';IF(ir_lines(7DOWNTO4)/=1110)THENnext_state=s4;next_state_value=0100;ELSECASEir_lines(3DOWNTO0)ISWHEN0001=--clazero_ac='1';load_ac='1';WHEN0100=--cmccm_carry_sr='1';WHEN1000=--aslalu_b='1';arith_shift_left='1';load_sr='1';load_ac='1';WHEN1001=--asralu_b='1';arith_shift_right='1';load_sr='1';load_ac='1';WHENOTHERS=NULL;ENDCASE;next_state=s2;next_state_value=0010;ENDIF;WHENs4=----------------------------------------4--readmemoryintomaroffsetmar_on_adbus='1';read_mem='1';databus_on_dbus='1';dbus_on_mar_offset_bus='1';load_offset_mar='1';IF(ir_lines(7DOWNTO6)/=11)THENir_on_mar_page_bus='1';load_page_mar='1';IF(ir_lines(4)='1')THENnext_state=s5;next_state_value=0101;ELSEnext_state=s6;next_state_value=0110;ENDIF;ELSE--jsrorbra,donotaltermar--pageIF(ir_lines(5)='0')THEN--jsrnext_state=s7;next_state_value=0111;ELSEnext_state=s9;next_state_value=1001;ENDIF;ENDIF;increment_pc='1';WHENs5=---------------------------------------5--readactualoperandfrommemoryintomar--offsetmar_on_adbus='1';read_mem='1';databus_on_dbus='1';dbus_on_mar_offset_bus='1';load_offset_mar='1';next_state=s6;next_state_value=0110;WHENs6=--------------------------------------6IF(ir_lines(7DOWNTO5)=100)THEN--jmpload_page_pc='1';load_offset_pc='1';next_state=s2;next_state_value=0010;ELSIF(ir_lines(7DOWNTO5)=101)THEN--maronadbus,acondatabus,write--tomemorymar_on_adbus='1';alu_b='1';obus_on_dbus='1';dbus_on_databus='1';write_mem='1';next_state=s1;next_state_value=0001;ELSIF(ir_lines(7)='0')THEN--------lda,and,add,sub--maronadbus,readmemoryfor--operand,performoperationmar_on_adbus='1';read_mem='1';databus_on_dbus=