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声明：本讲义内容用于内部交流和学习，请注意保护作者的版权集成电路测试方法研究华中科技大学IC设计中心陈新武声明：本讲义内容用于内部交流和学习，请注意保护作者的版权I目录摘要··················································································IAbstract················································································II1序言1.1背景及其意义···································································(1)1.2国内外研究现状·······························································(3)1.3本文的主要内容·······························································(5)2集成电路可测试性设计的基本概念2.1DFT的基本概念······························································(6)2.2DFT的常用方法······························································(6)2.3系统芯片与IP核·····························································(10)2.4自动测试设备（ATE）·····················································(11)2.5集成电路可测试性设计的挑战············································(12)3边界扫描测试方法3.1边界扫描基本状况···························································(14)3.2IEEEStd1149.1······························································(14)3.3IEEEStd1149.4······························································(16)3.4IEEEStd1149.5······························································(18)3.5IEEEStd1149.6······························································(20)3.6边界扫描测试的发展前景··················································(22)3.7本章小结·······································································(22)4全扫描可测试性实现方法4.1为什么需要扫描测试·························································(23)4.2可扫描单元类型·······························································(24)4.3如何提高故障覆盖率·························································(28)4.4一个实现实例·································································(41)声明：本讲义内容用于内部交流和学习，请注意保护作者的版权II4.5本章小结········································································(42)5集成电路的低功耗DFT方法5.1测试模式下功耗比较高的原因·············································(43)5.2基于扫描设计的低功耗DFT方法·········································(44)5.3基于非扫描设计的低功耗DFT方法······································(47)5.4本章小结········································································(52)6测试调度问题6.1为测试调度问题建立数学模型·············································(53)6.2解析测试基准电路ITC’02··················································(56)6.3测试调度算法··································································(61)6.4实验数据的构造·······························································(64)6.5实验结果与分析·······························································(65)6.6本章小结········································································(66)7总结与展望7.1总结·············································································(68)7.2本文的创新点·································································(69)7.3展望·············································································(69)参考文献············································································(72)附录1一个测试基准举例·····················································(78)声明：本讲义内容用于内部交流和学习，请注意保护作者的版权11序言本课程目的在于研究集成电路的测试实现方法，可以用于指导集成电路的设计工作。1.1背景及其意义随着集成电路制造技术和复杂度的提高，集成电路设计工程师可以将一个系统集成在一个芯片中，其中可能包括逻辑部分、存储器、模拟部分、模数混合部分等等，这样的系统称为片上系统，也称为系统芯片（SoC）。相对于板上系统，系统芯片极大地缩小了系统体积，减少了板级系统中芯片与芯片之间的互连延迟，从而极大地提高了系统的性能。为了缩短上市时间和节约开发成本，系统芯片越来越多的采用嵌入式核进行设计，这些嵌入式核被称为IP（IntellectualProperty）核，这种基于库资源的IP复用设计方式将成为IC设计的主流方式[1]。但是基于IP核的系统芯片设计方法也给设计者提出了更多的挑战，可测试性设计就是其中的难题之一。IEEE与JTAG于1990年提出了JTAG标准，即IEEEStd1149.1[2]，用于解决芯片之间的互连测试。但是，芯片之间的互连除了简单的导线连接之外，还有电容耦合或者电感耦合方式等，为了解决这类互连测试问题，IEEE标准化组织又于1999年提出了IEEEStd1149.4[3]；模数混合系统的出现，使得原来的1149.1表现出某些不足，因此，该组织于2001年对1990年版本的1149.1进行了修订[4]。随着各芯片之间的信号传输速度的提高(高达数GHz)，数字信号在这些通道上逐渐表现出模拟特性，为了能够对高速数字通道进行测试，该组织又于2004年推出了IEEEStd1149.6标准[5]。另外，该组织还提出了IEEEStd1149.5标准[6]。这些标准的出台，大大的推动了互连测试技术的发展。值得指出，边界扫描系列标准虽然是为了进行互连测试而提出的，它也可以应用于芯片内部的可测试性设计。只是由于芯片内部的测试需要较大的数据量，而边界扫描所提供的扫描端口数目较少，所以在大多数情况下，它只用于芯片之间的互连测试。声明：本讲义内容用于内部交流和学习，请注意保护作者的版权2对于芯片内部的可测试性设计，主要采用扫描设计和BIST方法。Mentor公司和Synopsys公司的可测试性设计工具都支持这两种方法。但是现代的测试工具还有许多不够完善的地方，比如在BIST方面，它们都不能够实现测试向量生成器的分离，即：将一个测试向量生成器分成多个可以工作在不同时钟频率下的多个测试向量生成器，分别作用在不同的被测试模块的引脚上。扫描技术除了边界扫描之外，还包括全扫描和部分扫描。全扫描技术就是将芯片内部所有的触发器用可扫描触发器替换，而部分扫描则是将芯片内部的一部分触发器采用可扫描触发器替换。目前这项技术已经比较成熟，需要解决的只是一些细节问题，目的在于提高故障覆盖率和易测试性。BIST技术是一种内建自测试技术，对于它的研究目前主要集中在低功耗和高故障覆盖率方面。系统芯片的测试自动化包括两个方面的内容，一个方面是系统芯片本身要具有高度的可控制性和可观测性，另一个方面就是要有功能强大的自动测试设备。以上所提到的问题都属于第一方面的问题。下面简单介绍第二方面的问题。自动测试设备需要将测试激励施加到被测试芯片，随着芯片复杂性的提高，测试数据量非常浩大，所以它应该有很大的内存（经常需要几十个吉字节）。为了缩短测试时间，就要尽可能的让芯片内部各模块进行并行测试，如何让芯片在最短的时间内完成测试，又要保证各项资源不冲突，是一个困难的问题。为了缩短测试时间，要考虑到很多因素，下面列出几个最重要的问题：（1）功耗约束问题：系统芯片各个模块在并行测试时，功耗往往很高，所以必须确定功耗极限值，这个极限值的确定往往与芯片的材料、电路的性质等多种因素有关；（2）TAM优化问题：自动测试设备往往要提供大量的测试总线，如何将测试总线分配给相应的被测试模块，缩短测试时间，是一个困难的问题；（3）优先级问题：系统芯片中各个模块的测试并非完全独立，外层模块的测试有时需要它的嵌入式模块先完成测试；声明：本讲义内容用于内部交流和学习，请注意保护作者的版权3（4）资源冲突问题：测试资源包括内部与外部的各种总线、激励产生单元、响应分析器等。在并行测试期间，同一个测试资源不能在同一时刻分配给不同的测试模块，同一个模块也不能同时分配给不同的测试资源。（5）故障模型的复杂性：现代的自动测试设备往往只能测试固定型故障，对于电流故障模型的测试大多不能胜任。虽然有些测试设备可以实现电流模型的测试，但是目前的技术水平仍然不能准确确定故障位置。由于目前的自动测试设备很难处理好以上问题，特别是测试调度问题，我们希望通过自己的努力，在测试调度领域做出一点有益的尝试。鉴于以上种种情况，在国家自然基金的资助下，我们开展了一系列的工作