毕业设计(论文)题目基于FPGA的函数信号发生器设计系(院)物理与电子科学系专业电子信息科学与技术班级学生姓名姜波学号指导教师李卫兵职称副教授二〇一三年六月十八日独创声明本人郑重声明:所呈交的毕业设计(论文),是本人在指导老师的指导下,独立进行研究工作所取得的成果,成果不存在知识产权争议。尽我所知,除文中已经注明引用的内容外,本设计(论文)不含任何其他个人或集体已经发表或撰写过的作品成果。对本文的研究做出重要贡献的个人和集体均已在文中以明确方式标明。本声明的法律后果由本人承担。作者签名:二〇一三年六月十八日毕业设计(论文)使用授权声明本人完全了解关于收集、保存、使用毕业设计(论文)的规定。本人愿意按照学校要求提交学位论文的印刷本和电子版,同意学校保存学位论文的印刷本和电子版,或采用影印、数字化或其它复制手段保存设计(论文);同意学校在不以营利为目的的前提下,建立目录检索与阅览服务系统,公布设计(论文)的部分或全部内容,允许他人依法合理使用。(保密论文在解密后遵守此规定)作者签名:二〇一三年六月十八日本科毕业设计(论文)I基于FPGA的函数信号发生器设计摘要函数信号发生器在教学、通信、测量等领域是非常重要的的工具。制作噪声低、频率变换快和分辨率高的信号发生器已引起了现科学界越来越浓厚的兴趣。由于直接数字频率合成技术(DDS)的各种优点,因此带来了电子科学界频率合成的革命。本设计主要讨论了如何利用FPGA来实现一个DDS系统,该系统以FPGA为核心的硬件结构来实现,使用Altera公司的CycloneII系列开发板。通过对时钟信号进行分频和相位累加,对输出的波形进行调用LPM-ROM存储,再经高速D/A转换,低通滤波器后输出函数信号。通过对QuartusII开发工具的VHDL的编写,电路的连接,时序仿真进行了研究。而且利用ModelSim进行更精确地仿真。仿真通过后,形成顶层文件得以完成对系统的全面布局,最后将软件硬件互相结合,下载到开发板FPGA芯片上进行硬件调试。利用变化的八位控制字实现了正弦波、三角波、方波在1Hz-10MHz的可调输出,利用除法器控制实现波形在0-5V的幅度调节。关键词:现场可编程门阵列;直接数字频率合成技术;VHDL语言;数模转换本科毕业设计(论文)IIFPGA-basedFunctionSignalGeneratorDesignAbstractFunctiongeneratorisaveryindispensabletoolincommunications,measurement,teachingandotherfields.Soproductionfrequencyswitching,highresolutionandlownoisesignalgeneratorfunctionhascausedgrowinginterestinthescientificcommunity.BecauseoftheDirectDigitalSynthesis(DDS)technologyhasmanyadvantages,thescientificcommunityhasbroughtarevolutionfrequencysynthesizer.ThisdesignfocusonhowtousetheFPGAtoimplementaDDSsystem,whichisthecoreoftheFPGAhardwarearchitecturetoachieve,usingAltera'sCycloneIIdevelopmentboardseries.Throughtheclocksignalfrequencyandthephaseaccumulator,theoutputwaveformisstored,andthentheD/Aconverter,theoutputlow-passfilterfunctionsignal.ThroughtheQuartusIIdevelopmenttoolstowriteVHDL,circuitconnection,timingsimulationwerestudied.AndtheuseofmoreaccuratesimulationwithModelSim.Throughsimulation,theformationofthetop-levelfilesystemtocompletetheoveralllayout,andfinallythecombinedhardwareandsoftware,downloadedtotheFPGAchipdevelopmentboardforhardwaredebugging.Usechangesineightcontrolwordstoachieveasinewave,trianglewave,squarewaveat1Hz-10MHzadjustableoutput,thewaveformusingthedividercontrolthemagnitudeofthe0-5Vregulator.Keywords:Field-ProgrammableGateArray;DirectDigitalSynthesizer;Very-High-SpeedIntegratedCircuitHardwareDescriptionLanguage;Digitaltoanalogconverter本科毕业设计(论文)i目录引言.................................................................................................................................1第一章DDS技术与原理..................................................................................................21.1DDS相关技术..............................................................................................................21.2DDS的基本原理..........................................................................................................2第二章FPGA及编程环境...............................................................................................52.1FPGA的基本原理........................................................................................................52.2编程软件—QuartusII...................................................................................................6第三章系统方案论证.......................................................................................................73.1系统总体方案设计.......................................................................................................73.2系统方案论证与选择...................................................................................................83.2.1总体方案论证与比较................................................................................................83.2.2DDS模块方案论证...................................................................................................83.2.3数据存储方案论证....................................................................................................93.2.4键盘/显示方案论证...................................................................................................93.2.5数模转换方案论证....................................................................................................93.2.6滤波方案论证..........................................................................................................10第四章DDS的FPGA实现...........................................................................................114.1主程序流程图.............................................................................................................114.2各单元内部模块设计.................................................................................................124.2.1分频模块的设计......................................................................................................124.2.2累加器模块的设计..................................................................................................124.2.3波形存储模块的设计..............................................................................................134.2.4幅度调节的设计......................................................................................................144.2.5mif文件设计...........................................................