Disturb Testing in Flash Memories

NationalAeronauticsandSpaceAdministrationDisturbTestinginFlashMemoriesDouglasSheldonJetPropulsionLaboratoryCaliforniaInstituteofTechnologyPasadena,CaliforniaMichaelFreieSemiconductorSolutions,Inc.Sparks,NevadaJetPropulsionLaboratoryCaliforniaInstituteofTechnologyPasadena,CaliforniaJPLPublication08-73/08NationalAeronauticsandSpaceAdministrationDisturbTestinginFlashMemoriesNASAElectronicPartsandPackaging(NEPP)ProgramOfficeofSafetyandMissionAssuranceDouglasSheldonJetPropulsionLaboratoryCaliforniaInstituteofTechnologyPasadena,CaliforniaMichealFreieSemiconductorSolutions,Inc.Sparks,NevadaNASAWBS:939904.01.11-10JPLProjectNumber:102197TaskNumber:1.23.6JetPropulsionLaboratory4800OakGroveDrivePasadena,CA91109(NEPP)Program.Referencehereintoanyspecificcommercialproduct,process,orservicebytradename,trademark,manufacturer,orotherwise,doesnotconstituteorimplyitsendorsementbytheUnitedStatesGovernmentortheJetPropulsionLaboratory,CaliforniaInstituteofTechnology.Copyright2008.Allrightsreserved.iiiTableofContentsExecutiveSummary........................................................................................................................1Introduction.....................................................................................................................................2ReviewofFlashMemoryTechnology...........................................................................................2NANDFlashMemoryOperation....................................................................................................6NANDFlashErrorsModes............................................................................................................7DisturbErrors..................................................................................................................................8BadBlocks....................................................................................................................................10DeviceProgrammingDetails........................................................................................................11ExperimentalResults....................................................................................................................14Conclusions...................................................................................................................................20References.....................................................................................................................................211/26DisturbTestingFlashMemoriesSheldonExecutiveSummary2GbNANDflashdevicesweretestedforsensitivitytobothprogramandreaddisturbconditions.ThisdisturbtestingispartoftheoverallreliabilityevaluationofthesedevicesforuseonNASAmissions.Radiationevaluationforthesedeviceshasalreadybeendocumented[Irom].Disturbtestingisdesignedtostudytherobustnessofthedatastorageoftheflashcellswhenthestateofanearbycellisbeingchanged,eitherthroughprogrammingorreading.Adisturbfailuremeansthattheinitial(andexpected)stateofthecellhasbeenchanged(disturbed)totheoppositestateasaresultofprogrammingorreadingthenearbycells.Disturbfailuresareusuallysoftfailuresthatrequireadditionaldevicecommandstorepair.Flashmanufacturersacknowledgedisturbfailurescanoccurontheirdevicesandtrytoprovideuserswithguidanceonhowtoaddressthem.ForthehighreliabilitynatureofNASAmissions,aquantitativeunderstandingofthepossibledegreeofdisturbfailuresisrequired.Suchquantitativeunderstandingwillguidedevicescreeningandprocurementrequirementsaswellaspossiblesystemmitigationimplementations.Nospecificdisturbfailureswerenotedonthetestingdoneforthisreport.However,inconsistentbehaviorinflashmemorybadblockswasobserved.Blocklocationsthatwereinitiallyidentifiedasbadbythemanufacturerperformedcorrectlyasthedevicebegantobeexercised.Theselocationsremainedrobustevenasthedevicewasstressedovertimeandtemperature.Othercellsmarkedasgoodbythemanufacturerbegantodegradeunderthisexposuretotimeandtemperature.Theassociatedfailureratewiththisdegradationis100Xhigherthanpredictedbythemanufacturer’sdata.Atthistime,itisunknownwhysuchahighfailureratewasobserved.Theexistenceofthismuchhigherfailurerateandinconsistencyinmanufacturer-definedbadandgoodblocksmeansthatNASAmustindividuallyscreen,characterize,andqualifyanyandallNANDflashdevicesthatitintendstouseforspacecraftapplications.2/26DisturbTestingFlashMemoriesSheldonIntroductionNon-volatilememorytechnologyasdefinedbyNANDarchitectureflashmemorycontinuestoleadtheprocessscalinganddeviceshrinkingeffortsoftheentireintegratedcircuitindustry.45-nmtechnologynodesarenowproducingcommercial32Gbdevices.Theselatest32Gbdevicesarepioneeringnewchargetrappingmemorycelltechnologiesusingmetalgatesandhigh-kdielectricmaterials.ThesecellsarecalledTANOSandconsistoftantalum-nitride,aluminumoxide(highkmaterial),nitride,oxide,andsili