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摘要本设计实现多路数据时分复用和解复用系统。设计分为发端和收端，以FPGA作为主控核心。发端系统有三路并行数据输入：A/D转换数据，拨码开关1路和拨码开关2路。这三路数据在FPGA的控制下作为串行码分时输出。发端FPGA包括分频模块、复用模块和电压显示模块。在收端，串行数据进入FPGA，并由FPGA提取位时钟，识别帧同步并解复用发端打包的三路码。收端的FPGA包括数字锁相环模块、解复用模块和电压显示模块。发端FPGA输入有三路8-bit数据：第一路为A/D数据、第二路和第三路是拨码开关产生的数据，另外插入一路巴克码。这四路码组成一帧，由FPGA对其时分复用。A/D输入端的模拟信号的电压值通过FPGA处理，显示在数码管上。在收端，FPGA首先提取位同步，然后识别帧同步，一旦识别出帧同步，FPGA分别解复用三路数据。本文详细阐述了此系统的设计方法，制作过程以及制作过程中的问题。设计者的工作包括：系统各部分电路元件的确定、确定系统框图、画出系统原理图、根据原理图设计FPGA的RTL代码、综合、仿真RTL代码、设计PCB板和在线调试FPGA功能。关键字：数字锁相环；帧同步；时分复用；VerilogHDL语言；串行A/D变换；AbstractThesystemisdesignedfordatamultiplexedandde-multiplexed.ItisbasedonTDM.Thesystemincludesthetransmitterandthereceiver.TheyareimplementedmainlybyFPGA.Therearethreeinputsinthetransmissionsystem:datafromA/Dconverter,DIP1andDIP2.Thethreechannelsareoutseriallyandtime-divisionalundertheFPGA’scontrol.TheFPGAinthetransmitterisdividedintofourmoduleswhicharefrequencydivider,Barkergenerator,datamultiplexerandvoltagedisplay.VoltagedisplayisusedforprocessingthedataconvertedbyADCandsendingittotheLED.TheserialdataareserialshiftedintotheFPGAinthereceiver.Bit-synchronizeandframe-synchronizearebothpickedup,andthende-multiplex.TheFPGAinthereceiverisdividedintothreemoduleswhicharedigitalPLL,datade-multiplexerandvoltagedisplay.Thetransmitterwillmultiplexfourwaysof8-bitparalleldata.ThefirstwayisADCdata,thesecondandthethirdwayisgeneratedbydip-key.TheotherisBarkercodeusedforframesynchronizing.Thereceiverwillmaintainthebitsynchronizing,recognizeoneframeandde-multiplexthreewaysdata.Theessaywilldiscussthedesignprogress,theprogrammingideaandsomeproblems.Workshavetobedonebythedesignerare:Specifyallsystemcomponents,Makesystemspecification,Drawsystemschematics,WriteRTLcodeaccordingtheschematics,SynthesisandsimulatetheRTLcode,DesignthePCBs,ValidatethefunctionsoftheFPGAon-line.Keywords:DPLL;Frame-synchronize;TDM;VerilogHDL;SerialA/Dconvert;目录引言.................................................................................51数字复接系统简介..................................................................52数字复接方法及方式................................................................62.1数字复接的方法..................................................................62.2数字复接的方式..................................................................63系统原理和各模块设计..............................................................63.1系统原理及框图..................................................................63.2发端系统设计....................................................................73.3收端系统设计.....................................................................93.4FPGA的设计流程..................................................................113.4.1设计输入......................................................................113.4.2设计综合......................................................................123.4.3仿真验证......................................................................123.4.4设计实现......................................................................123.4.5时序分析......................................................................123.5发端FPGA设计....................................................................133.5.1分频模块......................................................................143.5.2复接模块......................................................................153.5.3显示模块......................................................................163.5.4编译与仿真....................................................................183.6收端FPGA设计....................................................................193.6.1数字锁相模块..................................................................203.6.2解复用模块....................................................................213.6.3显示模块......................................................................223.6.4编译与仿真....................................................................223.7数字锁相环原理及设计.............................................................233.8串行A/D工作原理..................................................................253.9并行D/A的工作原理................................................................263.10AlteraFlex10K10介绍.............................................................274系统调试.........................................................................325QuartusII软件及Verilog语言简介.....................................................325.1QuartusII软件简介.................................................................325.2Verilog语言简介..................................................................346结论.............................................................................35谢辞................................................................................36参考文献............................................................................37附录..............................................................................38目录引言11数字复接系统简介12数字复接方法及方式22.1数字复接的方法22.2数字复接的方式23系统原理和各模块设计23.1系统原理及框图23.2发端系统设计33.3收端系统设计53.4FPGA的设计流程73.4.1设计输入73.4.2设计综合83.4.3仿真验证83.4.4设计实现83.4.5时序分析83.5发端FPGA设计93.5.1分频模块103.5.2复接模块1