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September1993OrderNumber:270251-004MCSÉ51FamilyofMicrocontrollersArchitecturalOverviewInformationinthisdocumentisprovidedinconnectionwithIntelproducts.Intelassumesnoliabilitywhatsoev-er,includinginfringementofanypatentorcopyright,forsaleanduseofIntelproductsexceptasprovidedinIntel'sTermsandConditionsofSaleforsuchproducts.Intelretainstherighttomakechangestothesespecificationsatanytime,withoutnotice.MicrocomputerProductsmayhaveminorvariationstothisspecificationknownaserrata.*Otherbrandsandnamesarethepropertyoftheirrespectiveowners.²Sincepublicationofdocumentsreferencedinthisdocument,registrationofthePentium,OverDriveandiCOMPtrademarkshasbeenissuedtoIntelCorporation.ContactyourlocalIntelsalesofficeoryourdistributortoobtainthelatestspecificationsbeforeplacingyourproductorder.Copiesofdocumentswhichhaveanorderingnumberandarereferencedinthisdocument,orotherIntelliterature,maybeobtainedfrom:IntelCorporationP.O.Box7641Mt.Prospect,IL60056-7641orcall1-800-879-4683COPYRIGHT©INTELCORPORATION,1996MCSÉ-51FamilyofMicrocontrollersArchitecturalOverviewCONTENTSPAGEINTRODUCTIONÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1CHMOSDevicesÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2MEMORYORGANIZATIONINMCSÉ-51DEVICESÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2LogicalSeparationofProgramandDataMemoryÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2ProgramMemoryÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ3DataMemoryÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4THEMCSÉ-51INSTRUCTIONSETÀÀÀÀÀÀÀÀ5ProgramStatusWordÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ5AddressingModesÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ6CONTENTSPAGEArithmeticInstructionsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ6LogicalInstructionsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ8DataTransfersÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ8BooleanInstructionsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ10JumpInstructionsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ12CPUTIMINGÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ13MachineCyclesÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ14InterruptStructureÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ16ADDITIONALREFERENCESÀÀÀÀÀÀÀÀÀÀÀÀÀ183MCSÉ-51ARCHITECTURALOVERVIEWINTRODUCTIONThe8051istheoriginalmemberoftheMCSÉ-51family,andisthecoreforallMCS-51devices.Thefeaturesofthe8051coreare:#8-bitCPUoptimizedforcontrolapplications#ExtensiveBooleanprocessing(single-bitlogic)capabilities#64KProgramMemoryaddressspace#64KDataMemoryaddressspace#On-chipProgramMemory#128bytesofon-chipDataRAM#32bidirectionalandindividuallyaddressableI/Olines#Two16-bittimer/counters#FullduplexUART#6-source/5-vectorinterruptstructurewithtwoprioritylevels#On-chipclockoscillatorThebasicarchitecturalstructureofthis8051coreisshowninFigure1.270251±1Figure1.BlockDiagramofthe8051Core1MCSÉ-51ARCHITECTURALOVERVIEW270251±2Figure2.MCSÉ-51MemoryStructureCHMOSDevicesFunctionally,theCHMOSdevices(designatedwith``C''inthemiddleofthedevicename)areallfullycompatiblewiththe8051,butbeingCMOS,drawlesscurrentthananHMOScounterpart.TofurtherexploitthepowersavingsavailableinCMOScircuitry,twore-ducedpowermodesareadded:#Software-invokedIdleMode,duringwhichtheCPUisturnedoffwhiletheRAMandotheron-chipperipheralscontinueoperating.Inthismode,cur-rentdrawisreducedtoabout15%ofthecurrentdrawnwhenthedeviceisfullyactive.#Software-invokedPowerDownMode,duringwhichallon-chipactivitiesaresuspended.Theon-chipRAMcontinuestoholditsdata.Inthismodethedevicetypicallydrawslessthan10mA.Althoughthe80C51BHisfunctionallycompatiblewithitsHMOScounterpart,specificdifferencesbetweenthetwotypesofdevicesmustbeconsideredinthedesignofanapplicationcircuitifonewishestoensurecompleteinterchangeabilitybetweentheHMOSandCHMOSdevices.TheseconsiderationsarediscussedintheAp-plicationNoteAP-252,``Designingwiththe80C51BH''.Formoreinformationontheindividualdevicesandfeatures,refertotheHardwareDescriptionsandDataSheetsofthespecificdevice.MEMORYORGANIZATIONINMCSÉ-51DEVICESLogicalSeparationofProgramandDataMemoryAllMCS-51deviceshaveseparateaddressspacesforProgramandDataMemory,asshowninFigure2.ThelogicalseparationofProgramandDataMemoryallowstheDataMemorytobeaccessedby8-bitaddresses,whichcanbemorequicklystoredandmanipulatedbyan8-bitCPU.Nevertheless,16-bitDataMemoryad-dressescanalsobegeneratedthroughtheDPTRregis-ter.ProgramMemorycanonlyberead,notwrittento.Therecanbeupto64KbytesofProgramMemory.IntheROMandEPROMversionsofthesedevicesthelowest4K,8Kor16KbytesofProgramMemoryareprovidedon-chip.RefertoTable1fortheamountofon-chipROM(orEPROM)oneachdevice.IntheROMlessversionsallProgramMemoryisexternal.ThereadstrobeforexternalProgramMemoryisthesignalPSEN(ProgramStoreEnable).2MCSÉ-51ARCHITECTURALOVERVIEWDataMemoryoccupiesaseparateaddressspacefromProgramMemory.Upto64KbytesofexternalRAMcanbeaddressedintheexternalDataMemoryspace.TheCPUgeneratesreadandwritesignals,RDandWR,asneededduringexternalDataMemoryaccesses.ExternalProgramMemoryandexternalDataMemorymaybecombinedifdesiredbyapplyingtheRDandPSENsignalstotheinputsofanANDgateandusingtheoutputofthegateasthereadstrobetotheexternalProgram/Datamemory.ProgramMemoryFigure3showsamapofthelowerpartoftheProgramMemory.Afterreset,theCPUbeginsexecutionfromlocation0000H.AsshowninFigure3,eachinterruptisassignedafixedlocationinProgramMemory.TheinterruptcausestheCPUtojumptothatlocation,whereitcommences