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ISEModelsimFPGA 2012130 ISE_12.2,MODELSIM_6.5eISEMODELSIMMODELSIMISEnetgen 1.ISED:\timing_sim 2.ISEProject New Project Next, Next, Finish. ISEMODELSIM OK MODELSIM Compile HDL Simulation Libraries C:\Xilinx\12.2\ISE_DS\ISE\bin\nt ISEMODELSIM Next, Next, Next, Next, ISEmodelsim.ini,ISEmodelsim.ini,C:\Xilinx\12.2\ISE_DS\ISE\bin\ntMODELSIMmodelsim.iniMODELSIMmodelsim.ini,C:\modeltech_6.5e ISEmodelsim.iniCOPYMODELSIMmodelsim.iniMODELSIMmodelsim.iniCOPYISEmodelsim.iniLaunch Compile Process COPYMODELSIMmodelsim.ini ISEMODELSIMMODELSIM ViewImpementation,ViewSimulationImpementation AssociationImplementation,OK AssociationSimulation,ViewSimulation Post‐Route Simulate Post‐Place & Route Model MODELSIMImplementationMODELSIMISEMODELSIM WAVEMODELSIMISEWAVEOPENwave.doWAVErun 2000 ns. 1implementation D:\timing_sim\counter\netgen\par D:\timing_sim\counterISEISEMODELSIMMODELSIMMODELSIMMODELSIM D:\timing_sim\MODELSIM_TEST,ISEnetgennetgenMODELSIMD:\timing_sim\MODELSIM_TEST MODELSIMD:\timing_sim\MODELSIM_TEST TOPMODULETOPMODULE OK Add Existing File,D:\timing_sim\MODELSIM_TEST\netgen\par counter_timesim.vISE OK OK SDF Librarywork work glbl, SDF Apply to RegionMODULE/ glbl OKSIGNALWAVE dutduttest_counter counter.v: module counter (count, clk, reset); output [7:0] count; input clk, reset; reg [7:0] count; always @ (posedge clk or posedge reset) if (reset) count = 8'h00; else count = count + 8'h01; endmodule tcounter.v `timescale 1ns/10ps module test_counter; reg clk, reset; wire [7:0] count; counter dut (.count(count), .clk(clk), .reset(reset)); initial // Clock generator begin clk = 0; forever #20 clk = !clk; end initial // Test stimulus begin reset = 0; #5 reset = 1; #4 reset = 0; end endmodule