基于FPGA的交流电机矢量控制系统的实现

华中科技大学硕士学位论文基于FPGA的交流电机矢量控制系统的实现姓名：李树庭申请学位级别：硕士专业：电力电子与电力传动指导教师：许强20080609IEDACPLD/FPGA,,(FPGA)(FOC),(SVPWM)TopdownFPGAIIABSTRACTThedevelopmentofmodernmotorcontroldemandsimprovementofperformance,reductionofthelossanddecreaseinthecost.Ontheotherhand,qualificationsandhardspecialapplicationssystemdemandsareraised.Therefore,researchofintegrateddesignforcontrollerbasedonEDAtechniqueandCPLD/FPGAdevice,whichmakesuseofmoderncontroltheory,isoneofthegreatdirectionsofthedevelopmentofmotorcontrolfield.Notonlyisitofacademicsignificance,itisofgreateconomicalandstrategicallysignificanceaswell.Itwillbepopularforbothmilitaryandciviluse.onthebasisoftheMathematicalmodelofpermanentmagneticsynchronousmotorandthetheoryofvectorcontrol,adigitalmotorcontrolsystemrealizedononechipFPGA,hasbeendesignedinthisthesis.Theimplementationoffunctionalmodules,suchaspositionmeasurement,PIregulator,vectortransformation,SVPWMandcommunicationisproposed.Meanwhile,designsofsomeperipheralinterfacesaregiven.Thusaone-chipmotorcontrolleriscarriedout.Simulationsandexperimentalanalysesarecarriedon.Tosavethechipresource,thoughtsoftime-sharingandareappliedinthedesignofsinelookuptableunitanddutyrationcalculatingunit.Theexperimentalresultisgivenatlast.ThissystemcompletesthevectorcontrolalgorithmanditalsocanbeappliedaspartofaPositioncontrolsystemTheprojectusesTopdowntechnologytodevelopcorebydividingsystemaccordingtoit'sfunction.Atfirst,designandsimulateonsinglemodule,secondly,onthewholesystem,atlastverificationusingFPGA.Theresultsprovedthedesignschemeisreliableandperfectonfunction.Keyword:FOCFPGAServoControl______111.1DSP[3,4]CPUDSP(FPGA)EDAASICFPGAICCPUFPGADSPCPUFPGACPU(XILINXVETEX)FPGASoPCFPGA(FOC)EDA:1.FPGAFOCSVPWM/SPWMPI22.FPGAIP(IntellectualProperty):3.FPGAPCB;EDAIPFPGAASICIPASIC1.21.2.1.3(DSP)DSP;DSPDSPDSPDSPDSPMCUDSPEDACPLD/FPGAEDAMCUDSPCPLD/FPGAEDACPLD/FPGAIPMCUMPUDSPA/DD/ARAM//IPCPLD/FPGA(ASIC),,,FPGA4,FPGA[1,2]FPGA[1]PI;[2][3]XilinxFPGA[4]MicroBlazeFPGA[5,6,7]FPGA1.2.2EDA(VLSI):EDA(ASIC)(SOC)EDA2090(CAD)(CAM)(CAT)(CAE)EDAVery-High-SpeedHDLVerilogHDLVHDLIP(FPGA)5(CPLD)EDAFPGACPLDEDACadenceDataI/OMentorGraphicsSynopsysViewlogicEDAEDAVHDL1982Very-High-SpeedIntegratedCircuitHardwareDescriptionLanguage1987VHDLIEEE(TheInstituteofElectricalandElectronicsEngineers)1993IEEEVHDLVHDLIEEE1076-1993VHDLVHDLC()()()VHDLVHDL;VHDLEDAVHDLIEEEVHDL(IEEE-1076)EDAVHDLVHDLXilinxFPGA1.2.3IPSOCIP(IntellectualProperty)ICIP(IP)(VC,VirtualComponent)IPIPIP6HDLVHDLVerilogHDLIPIPIPInternetIPIPIPIPIPIPIPIP(SOC)EDASOCPLDAlteraCPLDXilinxFPGAPLD1985XilinxFPGAFPGA100070.15um6XilinxFPGASPARTAN3ESPARTAN3ANVETEX-5VETEX-5DSPDSPCPLDFPGADSPSystemOnaChipSOCEDASOCEDA1-1EDA1-1EDA8FPGAASICASIC/ASSPFPGA2003ASIC3000FPGA80000XilinxSpartan——Spartan-3E102FPGAASICASICNREIPEDAASICFPGAFPGAIC1.3(Xilinx,Inc.)(AvnetElectronicsMarketing)FPGAXilinxIP:1.92.3.IP4.RTL:EDA5.6.1022.11972F.BlaschkePMSMa)b)c)d)[8][9][10]2.22-1PMSMasbscs120dd-q2-2PMSMd-qPMSMdddeqqqqedvRipvRipψωψψωψ=+−=++(2-1)dddfqqqLiLiψψψ=+=(2-2)112-1PMSM2-2PMSMdvqvdiqidψqψd-qRdLqLd-qeωfψ/pddt=()()3322epdqqdpfqdqdqTNiiNiLLiiψψψ=−=+−(2-3)eLrrTTBJpωω=++(2-4)d-qerNpωω=(2-5)pNeTLTJBrωa-b-cd-q:12cossin122cossin13322cossin133adbqcθθππθθοππθθ−=−−−+−+(2-6)22coscoscos33222sinsinsin333111222daqbcππθθθππθθθο−+=−−−−+(2-7)θda:()cos2cos32cos3ambmcmiIiIiIθβπθβπθβ=+=+−=++(2-8)d-qcossindmqmiIiIββ==(2-9)βdmI:13()cos2cos32cos3ambmcmvVvVvVθβπθβπθβ=+=+−=++(2-10)d-qcossindmqmvVvVββ==(2-11)βdmV()32eaabbccddqqPvivivivivi=++=+(2-12)SPMdqLLL==(2.3)eTetqTki=(2-13)32ftpkNψ=/0//0//01/0001/1/qdprdprpfqrtrdLqiRLNipiNRLNLikJBJLvTLvJωωψωω−=−−−−++−(2-14)rωdiqi142.3PMSM(VectorControlSystem)[11][12]()[13][14]bcaiii-iαiβdiqididqiqdiqi2-32-315:3/23/2Clarke:111222330322111222AB0Ciiiiiiαβ−−=−(2-15)2/3(Clarke):110221313222131222ABC0iiiiiiαβ=−−−(2-16)ParkParkParkPark:cossinsincosdqiiiiαβθθθθ=−(2-17)2.4PWMPWM16PWMSPWMCHPWMSPWM2.4.1SPWMSPWMSPWMSPWMSPWMFPGA2.4.2PWMPWMPWMPWMPWMPWMPWMD17PWM2.4.3PWMSVPWMSPWMPWM2/34/32()3jjiabcDCSSeSeVππν=++(2-18)aSbScSabcSSS882467(111)oνν(000)PWMrefν18)100()110()010()011()001()101(refsTν⋅4v→44Tν⋅66Tν⋅2v→3v→1v→6v→αβ5v→2424refνrefνrefν4ν6νPWMTs4ν6ν4T6T0T7T44660077()refTsdtTTTTννννν=⋅+⋅++∫4607()sTTTTT=+++(2-20)(2-19)070νν==PWMTsrefvrefrefsTsdtTνν=⋅∫(2-21)(2-19)(2-21)4646refssTTTTννν=+(2-22)refν4ν6ν(2-22)αβ−192-5θ60°αβrefανrefβν4(100)ν6(110)νrefν44sTTν66sTTν2-56644cos(30)(60)refsrefrefsTTTTtgββαννννν=°=+°(2-23)4623DCVνν==46(33)23srefrefDCsrefDCTTVTTVαββννν=−=(2-24):(i)46sTTT+≤0746()/2sTTTTT==−−(2-25)(ii)46sTTT+,2-620SbSaSc0T4T6T7T7T6T4T0T4ν0ν6ν7ν7ν6ν4ν0νsTsT2-6refν2.5PIPIDPIDDPIPI()()()01tPIutKetetdtT=+∫(2-26)()ut()etpKITTiTt00()tijjtiTetdtTe===∑∫(2-27)(2-27)(2-26)PI210[]iipijjITuKeeT==+∑(2-28)iuiieiPI(2-28)PIii-1(2-28)