基于FPGA的分布式光纤测温系统

太原理工大学硕士学位论文基于FPGA的分布式光纤测温系统姓名：胡玉良申请学位级别：硕士专业：@指导教师：董冠军@THESYSTEMOFOPTICALFIBERDISTRIBUTEDTEMPERRATUREMEASUREMENTBASEDONFPGAABSTRACTTheopticalfiberdistributedtemperaturemeasurementwhichbasedonthefiberRamanbackscatteringsystemisasensorsystemwhichmeasurereal-timedistributedtemperaturefieldofspace.ItisusedastemperaturesensorandtransitionmediumbyoneopticalfibermeasuringtemperatureofopticalfiberbasedonthetemperatureaffectofRamanbackscattering.ItalsocalculatesthepositionwhichismeasuedbyOTDR.Inthispaper,ontheprincipleofdistributedfiber-optictemperaturemeasurementsystembasedonRamanscattering,combinedwithFPGAandNiosIIembeddedsoft-coreprocessorwhichareproducedbyAltera,oneSOPCsolutionisadvanced.AccordingtothesolutionCycloneIIIseriesEP3C25producedbyAlterain2007isadopted,OpticalsignalswhichiscollectedfromthesceneistransmittedtoAPDwhichtransformsopticalsignalsintoelectricalsignals,throughamplifierelectricalsignalswhichtransformsintoLVDSdifferentialsignaltransmittedtothetwo-wayparallelhigh-speedADC08D500.ThusOutputsignaloffiber-optictemperaturesensorisacquiredunderthecontroloftwoNiosIIprocessorssignalsissavedintheinternalFIFOofEP3C25,thenthesedataistreatedbyinternalDspprocessingmodulescircuitryofEP3C25.EventuallyusfuldataistransmittedtothecomputerthroughtheUart.Thesedataisanalysedanddisplayedbythesoftwareonthecomputer.Thesystemismainlyfocusedondataprocessing,transmissionanddisplay.Averagefilteralgorithmisusedbysystemfordataprocessing,firstlythealgorithmisprovedrightforthesystem,thenMatlab'sDspBuildertoolsandQuartusIIsoftwareisusedbyDspmoduleforfunctionalsimulationandtimingsimulationthefeasibilityandreliabilityofDspmoduleisfullyverified.AfterdataisprocessedbyDspmodule,intheorderofPC,TheNiosIIprocessortransmitsdatathroughUarttoPC.Inthisarticle,variousmodules(Timer,DIO)whicharecontroledbyNiosIIprocessoraretestedandverified.Therelevantsoftwarecodeislistedintheappendix.AfterDspmoduleandNiosIIprocessoristested,ageneralschematicisprotracted;thecontentisdescribedindetailinchapter7.Afterprocessingandtransmisingdataisverified,thesoftwarecodesofcomputerarewritteninordertopreserveanddisplaydata.Theseelementsaredescribedindetailchapter6.Accordingtotherequirementsofoverallsystem,securityandflexibilityisalsoconsideredinthesoftware.ThehighlightofthesystemistheusageofFPGAdevicesfordataprocessing,thetwoadvantageofbeingflexibleandhigh-speedarecombined.SoitdoesbetterthanothertraditionalDspprocessorswhichfacedproblemsofbeinghigh-speed,non-reconfigurablehardwarestructureandlong-termdevelopmentperiodandnon-migrationthe.TheusageofPCsoftwarefordatapreservationanddisplaygreatlyenhancedinteractivefeatures,moreflexibilitytoconductvariouskindsofdataanalysisandsummary.KEYWORDS:RamanBackscattering,NiosIIProcessor,FPGA,SopcBuilder,DspBuilder1.1[3]uuuuu[2]uuuu1.21.2.1[3]LIOSCTM400012220KV3220KV5025001.5+/-1.51.2.21985J.P.Dankin[4]APDYORKKENTYORKGESOYORKPMTPMTYOPRGESO0.5PMTGESO[5]1.3AlteraCycloneIIISopcBuilderNiosIIFPGA[6]RayeighBrilloulnRamanRayeighBrillouln51km15m(mw)BrilloulnRamanBrilloulnBrillouln10~20GHz(50MHz)(10KHz)BrilloulnRamanRaman2.1SIO21=n2-11E2E0n0nh1E(2E)01nhE+(02nhE+)1E(2E)0n(Reyleigh)1E2Enn-0hnn-0(Stokes)2E0nh1Enn+0hnn+0(Anti-Stokes)1Enn±0Figure2-1energylevelofRaman-scattering2-2Figure2-2ThediagramofRaman-scattering’sspectralnctl2=ncv=tvncv=cnltll)2exp()(0∫=xlcsgfsdxSWvPzPaafPgvlsaa,lCSCSrn2225.0rCnNAS=l0lllΔ-0llΔ+0llllΔ+=0ssllllΔ-=0aaaIsI)(TR)/(exp4)/()(aKThcuIITRaSS-•==llhcukT)(TRT2.2FPGA1313APDNiosIIADFIFODspUartUSB2-3Figure2-3Overallsystemdiagram2-3AlteraCycloneIIIFPGADspLVDSADADC08D500500MSPS0.5m-45+85-20+8510.5m1s10km3.13.1.1]9[3.1.2]10[2gwVtwtgVpulseR2gwpulseVtR=gV)1005.2(8smVg×=)(10)(mnstRwpulse=fDAR)(100mfRDA≈ampR)(100mBRamp≈R]13[)(222mRRRRampDApusle++=3.1.3fNTmeas=ljgtgjgVlt2gV3.2maxTminTminmaxTTD-=(3-5)(3-5)[12])()()(tttNSX+=)(tS)(tN,,,3,2,1MjΛ=tΔ,1,,2,1,0-=KiΛji)()()(tjttjttjtiiiNSXΔ+Δ+Δ++=iti)(tSij)(tS)(tNijijjijNSX+=∑-===101KiiijjXKA)(tNNsijjijNSX+=jSNjiSSNRs=K∑∑∑-==-==-==+=101010KiiijKiijKiiijNSXjSKK)(tN[]⎥⎦⎤⎢⎣⎡+⎥⎦⎤⎢⎣⎡=++=∑∑∑-=+=-==-==-11202102)1(102KiimmjijKiiKiiijjKjjijNNENENNNENijNmjN2210NKiiijijKNENs=⎥⎦⎤⎢⎣⎡=∑-==NijKNs=2∑-===10KiijjKSSNjNjSKKKSSNRss==0KSNRSNRSNIRi==0KKSNIRKKSNR4-1Figure4-1TherelationshipbetweenSNIRandk(repeattimesofsampling)]14[∑==KiXKKA1i1KKSNIR=KKAKXKAKA)1()()1()(--+-=∑=--=KiKiXKA11)()1()(bbX(i)i10bbbKn22×12+=nSNIRLVDSFPGA5.1FPGA5.1.1APDAvalanchephotodiode7~8[15]nw[16]APD(APD)(102-104)[17]APD[16]APDAPD[15]CyOptics-27dBm10GAPD[18]10G10GInGaAsSiGe12.5GFEC10e-12-26dBm5-1Figure5-1APDRelevantparameters5-12~20nA1550nm-145-25-3Figure5-2TherelationshipofAPDbiasvoltageandoutputcurrent5-2Figure5-3Bandwidth’SflatnessofAPD5.1.2ADC08D500(NationalSemiconductorCorporation)ADC08D1000ADC08D1500ADC08D500/[19]500MSPS1.9v1.9WADC08D500500MSPS250MHz(ENOB)7.5BER10-18DNLLSB15.0±()(SNR)44.5dB()(SFDR)55dB()8(DES)1GSPS500MSPS-40+858/LVDSLQLVDS16SDRDDRADC500MSpsADC250MHzEP3C25(DDR)DDR125MHzCMOSFPGA180FPGASPIADC08D500LVDSDDRSDRADC08D5005.1.3®Cyclone®IIIFPGAAltera®CycloneCycloneIIIFPGAFPGAEP3C25(TSMC)65-nm(LP)CycloneIII65-nmFPGAC