PLL-training-workshop-比较详细

1TIClockingWorkshopJamesCatt,TimothyToroniSVA–SignalPathSolutionsJuly2012Overview1.NoiseTheory–Phasenoise&Jitter2.PLLTheory–WhyaPLL?3.DeterminingADCclockrequirements4.ChoosingPLLLoopBandwidth–Optimizingnoise5.DualLooporCascadedLoopArchitecture–Howdualloopshelp“cleanjitter”6.PCBlayoutguidelines23NoiseTheory•PhaseNoise•JitterNoiseinTimeandFrequencyDomaintimevoltageTimeDomainFourierTransformfrequencypowerFrequencyDomainf0{})(tvℑf0jitterphasenoisefrequencypowertimevoltage5PhaseNoiseintheFrequencyDomainFundamental,orcarrier,fCNoisesidebandsWidebandnoisefloorSpurious?Sφ(f)Inthefrequencydomain,thenoisyclockisnotanidealimpulse.Itappearsasaspikewithnoisesidebandsthatcausethebasetospread.OscillatorPhaseNoise6•1/fnnoisecomesfromsemiconductordevicesintheoscillatorcircuit•Broadband,flatnoiseisthermalnoiseLφ(f)=thesingle-side-bandphasenoisedensityfunctioninthefrequencydomain,expressedasdBc/Hz(dBc/Hz)Lφ(f)TheJitterFamilyTree7UnderstandwhattypeofjitterisimportanttotheapplicationUnderstandwhattypeofjitterisimportanttotheapplication8FrequencyDomainJitterMeasurementTimeDomainJitterMeasurementMeasuringPhaseNoiseandJitter8τRMS=√2∫Lφ(f)df2πf0f1f2f0,Carrier1.19nsp-pThetriggerthresholdis1mV,sothehistogramisoffsetfromzeroonthetimeaxisEven40GSoscilloscopeisnotrecommendedformeasuring316fsofrandomjitter!Notgoodfor1psrmsjittermeasurementsMeasurementofpeak-to-peakjitterofRMSnoiseisafunctionoftime.f1STARTf2STOP9PhaseNoisetoJitterconversion–graphicalinterpretation000000002)()(2)()(2)(ftttTTttπφτπφτπφ==⋅∴=Idealcrossingpointφφφφ(t0)israndomphaseerrorττττ(t0)israndomtimeerror00.250.50.7511.25(t0)T0=1/f02(t0)02fRMSRMSπστφ=∴RMSjitter,τRMS,isascaledversionofRMSphaseerror,σφ.())(2sin)(0000ttftvφπ+=InterpretationsofIntegratedPhaseError()∫⋅⋅212ffdffP()carrierfffdffP⋅⋅⋅∫π2221()⋅⋅⋅∫212log10ffdffP()∫⋅⋅212ffdffPNoiseTheory–TakeAways•FromPhaseNoisewecancalculateJitter,butnottheotherwayaround.•PhaseNoisequantifiesnoiseinthefrequencydomain.•Jitterquantifiesnoiseinthetimedomain.–AnintegrationbandwidthmustbedefinedforanRMSjittermeasurement!1112PhaseLockLoop(PLL)Theory•ClassicalPLL•WhyPLL?–FrequencyMultiplication–NoiseShaping•PLLPerformancePLLArchitecture•ThepurposeofaPLListophase-lockorfrequencylocktwooscillatorsthatmaybeoperatingatdifferentfrequencies.–Why?FrequencyAccuracy.JitterCleaning.•TheclassicPLLarchitectureincludes:–Referenceclock–Voltagecontrolledoscillator(VCO)withgainKVCO/s–ReferenceandFeedbackdividers–PhasedetectorandchargepumpwithgainKφ–Loopfilter[Z(s)]13RNFFandRFNFNFRFFREFOUTREFoutOUTREFPD=⋅=∴==MaximumPDF=GCD(FREF,FVCO)WhyVCOorVCXO•VCO–Wide-bandtuning–Poorfrequencyaccuracy–Highfrequenciesallowfrequencymultiplicationforachievingmanycustomeroutputfrequencies.14•VCXO(VoltageControlledCrystalOscillator)–VeryLowNoise–Notavailableathighfrequencies–Costincreaseswithfrequency15PLLAnalysis:LinearizedmodelNsHsKsZKsGVCO1)()()(=⋅⋅=φ()[])()(1)()()(sHsGsGxysGuysHyxu⋅+=∴⋅=⋅−=ClosedloopresponseSimplecontrolloop16PLLAnalysis:ClosedLoopBandwidth•PLLtransferfunctionintermsoftheloopparametersKφφφφ,Z(s),KVCO,andN.[]⋅⋅⋅+⋅⋅==⋅+=NsKsZKsKsZKsHsGsGVCOVCOinout1)(1)()()(1)(φφθθ•Loopbandwidth(ωωωω0)satisfiesthefollowingequality:NKKZNKKZNKKNjZKKsHsGVCOVCOVCOVCOjs1,,,)(1)(1)(1)()(00000000φφφφωωωωωωωω∝⇒⋅⋅=∴=⋅==⋅⋅⋅==⋅=17PhaseNoiseContributorsKRNPhaseDetector/ChargePumpVoltageControlledOscillatorVCOLoopFilterZ(s)divRefOscRCounterREFR-divPDLFKVCOSNCounterFoutRefClockEachfunctionalblockinthesynthesizercontributesnoise.Closed-loopanalysisyieldsthetransferfunctionforeachnoisesource,fromthenoiseinjectionpointtotheoutputofthesynthesizer18SummaryofSynthesizerNoiseTransferFunctions⋅+NsG1)(11⋅+⋅NsGsGR1)(1)(1⋅+NsGsG1)(1)(⋅+NsGsG1)(1)(⋅+⋅NsGsGK1)(1)(1φSourceTransferFunctionLowFreq.Approx.HighFreq.Approx.ResponseShapeVCO1/G(s),|1/G(s)|21HighpassReferenceOscillatorN/R,(N/R)2G(s),|G(s)|2LowpassRcounterN,N2G(s),|G(s)|2LowpassNcounterN,N2G(s),|G(s)|2LowpassPhaseDetectorN/Kφφφφ,(N/Kφφφφ)2G(s),|G(s)|2LowpassCourtesyofMr.BanerjeeFrequencyResponsesofNoiseSourcestoLoopFilter19VCOReferenceOscPLLffLoopBandwidthfN/RN/KΦ1OpenLoopFrequencyResponsesofNoiseSources20ReferenceOscPLLffOffsetFrequency(dBc/Hz)OffsetFrequency(dBc/Hz)OffsetFrequency(dBc/Hz)fLPLL_flat(f)=PN1Hz+20·log10(N)+10·log10(PDF)PN1HzdecreasesforhighchargepumpcurrentLPLL_1/fVCOSourcesofClosedLoopNoise21ThesizeoftheseregionswillchangedependingonloopbandwidthRefOSCPLLVCOLMK03806ImpactofPDF&NonPLLNoise(Simulation)22NarrowLoopBandwidth/VCOdominantloopfiltermayalsobegoodchoiceforhigherintegrationrangesPLLNoiseIntegrationLimitsPLLTheory–TakeAways•WhyauseaPLLtosettunableoscillatorfrequency,likeaVCO?•Feedbackisnecessarytoachievefrequencyaccuracyfrominputtooutput.•PLLnoiseperformancevariesuponconfiguration…-PhaseDetectorFrequencyisofprimarysignificanceforPLLnoiseperformance.(Maximizeforbestperformance)–MaximumPDF=GCD(FREF,FVCO)»12.288MHzreference
2500MHzVCOresultsin32kHzPDF»10MHzreference
2500MHzVCOresultsin10MHzPDF(312.5x)-ChargePumpCurrent.(Maximizeforbestperformance)•VCO/VCXOperformanceisfixed.Ifbet