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可编程ASIC设计实例电子科技大学通信与信息工程学院郭志勇附:占空比为70%的100分频器电路(将clk进行100分频,其中高低电平宽度为7:3)reg[7:0]count;always@(posedgeclk)beginif(~reset)begincount=0;clk_div100=1;endelsebeginif(count==99)begincount=0;clk_div100=1;endelsebeginif(count==69)begincount=count+1;clk_div100=0;endelsecount=count+1;endendend设计端口及需求:Clk(50MHz)resetsel0sel1sel2D0—D6ASIC设计实例D6D5D4D3D2D1D0D5D4D3D2D1D0位0位1位2位3位4位5段值位选0142574LS138sel0sel1sel2D0—D63数码管为共阴极设计需要知识点:1.如何分频?2.数码管动态显示原理及设计代码?3.芯片接口电路时序设计moduledisplay(clk,ledout,sel,reset);inputclk;inputreset;outputreg[6:0]ledout;outputreg[2:0]sel;reg[14:0]count;regclk_scan;reg[2:0]sel_temp;always@(posedgeclk)//??(50MHz-1KHz)beginif(~reset)begincount=0;clk_scan=0;endelsebeginif(count==25000)begincount=0;clk_scan=~clk_scan;endelsecount=count+1;endendalways@(posedgeclk_scan,reset)beginif(~reset)beginsel_temp=3'b000;endelsesel_temp=sel_temp+1;endalways@(posedgeclk)//???????beginsel=sel_temp;case(sel_temp)3'b000:ledout=7'b1111110;3'b001:ledout=7'b0110000;3'b010:ledout=7'b1101101;3'b011:ledout=7'b1111001;3'b100:ledout=7'b0110011;3'b101:ledout=7'b1011011;3'b110:ledout=7'b1011111;3'b111:ledout=7'b1110000;default:ledout=7'b0000000;endcase;endendmodule`timescale1ns/1nsmoduletestbench;//testmoduleregclk,reset;wire[6:0]ledout;wire[2:0]sel;parameterdely=10;displaytest(clk,ledout,sel,reset);always#(dely/2)clk=~clk;initialbeginreset=1;clk=0;#delyreset=0;#(dely*8)reset=1;endendmodulemodulecount(clk,ledout,sel,reset);inputclk;inputreset;outputreg[6:0]ledout;outputreg[2:0]sel;reg[14:0]count;regclk_scan;reg[3:0]dis_out_temp,one,two,three,four,five,six,seven,eight;reg[2:0]sel_temp;always@(posedgeclk)//分频(1KHz-0.1KHz)beginif(~reset)begincount=0;clk_scan=0;endelsebeginif(count==5)begincount=0;clk_scan=~clk_scan;endelsecount=count+1;endendalways@(posedgeclk)//产生扫描信号beginif(~reset)sel_temp=3'b000;elsesel_temp=sel_temp+1;endalways@(posedgeclk_scan,negedgereset)//第1位beginif(~reset)one=0;elsebeginif(one==9)one=0;elseone=one+1;endendalways@(posedgeclk_scan,negedgereset)//第2位beginif(~reset)two=0;elsebeginif(one==9&&two==9)two=0;elsebeginif(one==9)two=two+1;endendendalways@(posedgeclk_scan,negedgereset)//第3位beginif(~reset)three=0;elsebeginif(one==9&&two==9&&three==9)three=0;elsebeginif(one==9&&two==9)three=three+1;endendendalways@(posedgeclk_scan,negedgereset)//第4位beginif(~reset)four=0;elsebeginif(one==9&&two==9&&three==9&&four==9)four=0;elsebeginif(one==9&&two==9&&three==9)four=four+1;endendendalways@(posedgeclk_scan,negedgereset)//第5位beginif(~reset)five=0;elsebeginif(one==9&&two==9&&three==9&&four==9&&five==9)five=0;elsebeginif(one==9&&two==9&&three==9&&four==9)five=five+1;endendendalways@(posedgeclk_scan,negedgereset)//第6位beginif(~reset)six=0;elsebeginif(one==9&&two==9&&three==9&&four==9&&five==9&&six==9)six=0;elsebeginif(one==9&&two==9&&three==9&&four==9&&five==9)six=six+1;endendendalways@(sel_temp)//根据扫描值选择当前显示的位beginsel=sel_temp;case(sel_temp)3'b000:dis_out_temp=one;3'b001:dis_out_temp=two;3'b010:dis_out_temp=three;3'b011:dis_out_temp=four;3'b100:dis_out_temp=five;3'b101:dis_out_temp=six;3'b110:dis_out_temp=seven;3'b111:dis_out_temp=eight;default:dis_out_temp=eight;endcase;endalways@(dis_out_temp)//根据扫描值选择当前显示的位begincase(dis_out_temp)0:ledout=7'b1111110;//dis_out_temp=0;1:ledout=7'b0110000;//dis_out_temp=1;2:ledout=7'b1101101;//dis_out_temp=2;3:ledout=7'b1111001;//dis_out_temp=3;4:ledout=7'b0110011;//dis_out_temp=4;5:ledout=7'b1011011;//is_out_temp=5;6:ledout=7'b1011111;//dis_out_temp=6;7:ledout=7'b1110000;//dis_out_temp=7;8:ledout=7'b1111111;//dis_out_temp=8;9:ledout=7'b1111011;//dis_out_temp=9;default:ledout=7'b1111011;//dis_out_temp=7;endcase;endendmodule`timescale1ns/1nsmoduletestbench;//testmoduleregclk,reset;wire[6:0]ledout;wire[2:0]sel;parameterdely=10;counttest(clk,ledout,sel,reset);always#(dely/2)clk=~clk;initialbeginreset=1;clk=0;#delyreset=0;#(dely*8)reset=1;endendmodule设计一个交通灯信号控制电路。要求输入为1KHz的时钟和复位信号,输出为红、绿、黄三个信号(高电平为亮)。具体描述:复位信号(低电平)有效,红、绿、黄灯灭;接着进行如下循环:绿灯亮60秒,黄灯闪烁10秒(闪烁周期是1秒),红灯亮60秒。ASIC设计实例设计端口及需求:Clk(1KHz)resetGYRmodulelamp(reset,clk1k,R,G,Y);inputclk1k,reset;outputregR,G,Y;reg[9:0]count1;reg[18:0]count2;regclk1hz;always@(posedgeclk1k)begin//(1kHz-1Hz)if(~reset)begincount1=0;clk1hz=0;endelsebeginif(count1==500)begincount1=0;clk1hz=~clk1hz;endelsecount1=count1+1;endendalways@(posedgeclk1k,reset)if(~reset)begincount2=0;G=1'b0;Y=1'b0;R=1'b0;endelsebeginif(count2==129999)begincount2=0;endelsebeginif(count2=0&&count260000)beginG=1'b1;Y=1'b0;R=1'b0;count2=count2+1;endif(count2=60000&&count270000)beginG=1'b0;Y=clk1hz;R=1'b0;count2=count2+1;endelsebeginif(count2=70000)beginG=1'b0;Y=1'b0;R=1'b1;count2=count2+1;endelsebegincount2=count2+1;endendendendendendmodule附testbench代码`timescale100us/100usmoduletestbench;//testmoduleregclk,reset;wire[2:0]lamp_out;parameterdely=10;lamptest(reset,clk,lamp_out);always#(dely/2)clk=~clk;initialbeginreset=1;clk=0;#delyreset=0;#(dely*8)reset=1;endendmodule改进:加入倒计时模块设计端口及需求:Clk(1KHz)resetGYRD0—D6Sel段值位选moduleee(res
本文标题:ASIC设计实例(verilog)
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