Computer Organization and Design PPT3

COMPUTERORGANIZATIONANDDESIGNTheHardware/SoftwareInterface5thEditionChapter3ArithmeticforComputersChapter3—ArithmeticforComputers—2ArithmeticforComputersOperationsonintegersAdditionandsubtractionMultiplicationanddivisionDealingwithoverflowFloating-pointrealnumbersRepresentationandoperations§3.1IntroductionChapter3—ArithmeticforComputers—3IntegerAdditionExample:7+6§3.2AdditionandSubtractionOverflowifresultoutofrangeAdding+veand–veoperands,nooverflowAddingtwo+veoperandsOverflowifresultsignis1Addingtwo–veoperandsOverflowifresultsignis0Chapter3—ArithmeticforComputers—4IntegerSubtractionAddnegationofsecondoperandExample:7–6=7+(–6)+7:00000000…00000111–6:11111111…11111010+1:00000000…00000001OverflowifresultoutofrangeSubtractingtwo+veortwo–veoperands,nooverflowSubtracting+vefrom–veoperandOverflowifresultsignis0Subtracting–vefrom+veoperandOverflowifresultsignis1Chapter3—ArithmeticforComputers—5DealingwithOverflowSomelanguages(e.g.,C)ignoreoverflowUseMIPSaddu,addui,subuinstructionsOtherlanguages(e.g.,Ada,Fortran)requireraisinganexceptionUseMIPSadd,addi,subinstructionsOnoverflow,invokeexceptionhandlerSavePCinexceptionprogramcounter(EPC)registerJumptopredefinedhandleraddressmfc0(movefromcoprocessorreg)instructioncanretrieveEPCvalue,toreturnaftercorrectiveactionChapter3—ArithmeticforComputers—6ArithmeticforMultimediaGraphicsandmediaprocessingoperatesonvectorsof8-bitand16-bitdataUse64-bitadder,withpartitionedcarrychainOperateon8×8-bit,4×16-bit,or2×32-bitvectorsSIMD(single-instruction,multiple-data)SaturatingoperationsOnoverflow,resultislargestrepresentablevaluec.f.2s-complementmoduloarithmeticE.g.,clippinginaudio,saturationinvideoChapter3—ArithmeticforComputers—7MultiplicationStartwithlong-multiplicationapproach1000×100110000000000010001001000Lengthofproductisthesumofoperandlengthsmultiplicandmultiplierproduct§3.3MultiplicationChapter3—ArithmeticforComputers—8MultiplicationHardwareInitially0Chapter3—ArithmeticforComputers—9OptimizedMultiplierPerformstepsinparallel:add/shiftOnecycleperpartial-productadditionThat’sok,iffrequencyofmultiplicationsislowChapter3—ArithmeticforComputers—10FasterMultiplierUsesmultipleaddersCost/performancetradeoffCanbepipelinedSeveralmultiplicationperformedinparallelChapter3—ArithmeticforComputers—11MIPSMultiplicationTwo32-bitregistersforproductHI:most-significant32bitsLO:least-significant32-bitsInstructionsmultrs,rt/multurs,rt64-bitproductinHI/LOmfhird/mflordMovefromHI/LOtordCantestHIvaluetoseeifproductoverflows32bitsmulrd,rs,rtLeast-significant32bitsofproduct–rdChapter3—ArithmeticforComputers—12DivisionCheckfor0divisorLongdivisionapproachIfdivisor≤dividendbits1bitinquotient,subtractOtherwise0bitinquotient,bringdownnextdividendbitRestoringdivisionDothesubtract,andifremaindergoes0,adddivisorbackSigneddivisionDivideusingabsolutevaluesAdjustsignofquotientandremainderasrequired100110001001010-1000101011010-100010n-bitoperandsyieldn-bitquotientandremainderquotientdividendremainderdivisor§3.4DivisionChapter3—ArithmeticforComputers—13DivisionHardwareInitiallydividendInitiallydivisorinlefthalfChapter3—ArithmeticforComputers—14OptimizedDividerOnecycleperpartial-remaindersubtractionLooksalotlikeamultiplier!SamehardwarecanbeusedforbothChapter3—ArithmeticforComputers—15FasterDivisionCan’tuseparallelhardwareasinmultiplierSubtractionisconditionalonsignofremainderFasterdividers(e.g.SRTdevision)generatemultiplequotientbitsperstepStillrequiremultiplestepsChapter3—ArithmeticforComputers—16MIPSDivisionUseHI/LOregistersforresultHI:32-bitremainderLO:32-bitquotientInstructionsdivrs,rt/divurs,rtNooverflowordivide-by-0checkingSoftwaremustperformchecksifrequiredUsemfhi,mflotoaccessresultChapter3—ArithmeticforComputers—17FloatingPointRepresentationfornon-integralnumbersIncludingverysmallandverylargenumbersLikescientificnotation–2.34×1056+0.002×10–4+987.02×109Inbinary±1.xxxxxxx2×2yyyyTypesfloatanddoubleinCnormalizednotnormalized§3.5FloatingPointChapter3—ArithmeticforComputers—18FloatingPointStandardDefinedbyIEEEStd754-1985DevelopedinresponsetodivergenceofrepresentationsPortabilityissuesforscientificcodeNowalmostuniversallyadoptedTworepresentationsSingleprecision(32-bit)Doubleprecision(64-bit)Chapter3—ArithmeticforComputers—19IEEEFloating-PointFormatS:signbit(0non-negative,1negative)Normalizesignificand:1.0≤|significand|2.0Alwayshasaleadingpre-binary-point1bit,sononeedtorepresentitexplicitly(hiddenbit)SignificandisFractionwiththe“1.”restoredExponent:excessrepresentation:actualexponent+BiasEnsuresexponentisunsignedSingle:Bias=127;Double:Bias=1203SExponentFractionsingle:8bitsdouble:11bitssingle:23bitsdouble:52bitsBias)(ExponentS2Fraction)(11)(xChapter3—ArithmeticforComputers—20Single-PrecisionRangeExponents00000000and11111111reservedSmallestvalueExponent:00000001actualexponent=1–127=–126Fraction:000…00significand=1.0±1.0×2–126≈±1.2×10–38Largestvalueexponent:11111110actualexponent=254–127=+127Fraction