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ExamplesofVHDLDescriptionsAdvancedElectronicDesignAutomationExamplesofVHDLDescriptionsAuthor:IanElliottofNorthumbriaUniversityThisfilecontainsaselectionofVHDLsourcefileswhichservetoillustratethediversityandpowerofthelanguagewhenusedtodescribevarioustypesofhardware.Theexamplesrangefromsimplecombinationallogic,describedintermsofbasiclogicgates,tomorecomplexsystems,suchasabehaviouralmodelofamicroprocessorandassociatedmemory.AlloftheexamplescanbesimulatedusinganyIEEEcompliantVHDLsimulatorandmanycanbesynthesisedusingcurrentsynthesistools.Usethehierarchicallinksbelowtonavigateyourwaythroughtheexamples:●CombinationalLogic●Counters●ShiftRegisters●Memory●StateMachines●Registers●Systems●ADCandDAC●ArithmeticCombinationalLogic●Exclusive-ORGate(Dataflowstyle)●Exclusive-ORGate(Behaviouralstyle)●Exclusive-ORGate(Structuralstyle)●MiscellaneousLogicGates●Three-inputMajorityVoter●MagnitudeComparator●Quad2-inputNand(74x00)●BCDtoSevenSegmentDecoder●Dual2-to-4Decoder●OctalBusTransceiver●Quad2-inputOR●8-bitIdentityComparator●HammingEncoder●HammingDecoder●2-to-4DecoderwithTestbenchandConfiguration●Multiplexer16-to-4usingSelectedSignalAssignmentStatement●Multiplexer16-to-4usingConditionalSignalAssignmentStatement●Multiplexer16-to-4usingif-then-elsif-elseStatement●M68008AddressDecoder●HighestPriorityEncoder●N-inputANDGateCounters h t t p : / / w w w . a m i . b o l t o n . a c . u k / c o u r s e w a r e / a d v e d a / v h d l / v h d l e x m p . h t m l ( 1 o f 6 7 ) [ 2 3 / 1 / 2 0 0 2 4 : 1 5 : 0 1 ]●CounterusingaConversionFunction●GeneratedBinaryUpCounter●CounterusingMultipleWaitStatements●SynchronousDownCounterwithParallelLoad●Mod-16CounterusingJKFlip-flops●PseudoRandomBitSequenceGenerator●UniversalCounter/Register●n-BitSynchronousCounterShiftRegisters●UniversalShiftRegister/Counter●TTL164ShiftRegister●Behaviouraldescriptionofan8-bitShiftRegister●StructuralDescriptionofan8-bitShiftRegisterMemory●ROM-basedWaveformGenerator●AFirst-inFirst-outMemory●Behaviouralmodelofa16-word,8-bitRandomAccessMemory●Behaviouralmodelofa256-word,8-bitReadOnlyMemoryStateMachines●Classic2-ProcessStateMachineandTestBench●StateMachineusingVariable●StateMachinewithAsynchronousReset●PatternDetectorFSMwithTestBench●StateMachinewithMooreandMealyoutputs●MooreStateMachinewithExplicitStateencoding●MealyStateMachinewithRegisteredOutputs●MooreStateMachinewithConcurrentOutputLogicSystems●PelicanCrossingController●SimpleMicroprocessorSystem●BoothMultiplier●LotteryNumberGenerator●DigitalDelayUnit●ChessClockADCandDAC●PackagedefiningaBasicAnaloguetype●16-bitAnaloguetoDigitalConverter●16-bitDigitaltoAnalogueConverter●8-bitAnaloguetoDigitalConverter●8-bitUnipolarSuccessiveApproximationADC h t t p : / / w w w . a m i . b o l t o n . a c . u k / c o u r s e w a r e / a d v e d a / v h d l / v h d l e x m p . h t m l ( 2 o f 6 7 ) [ 2 3 / 1 / 2 0 0 2 4 : 1 5 : 0 7 ]●8-bitUnsignedMultiplier●n-bitAdderusingtheGenerateStatement●AVarietyofAdderStyles●BoothMultiplierRegisters●UniversalRegister●OctalD-TypeRegisterwith3-StateOutputs●QuadD-TypeFlip-flop●8-bitRegisterwithSynchronousLoadandClearUniversalRegisterDescription-Thisdesignisauniversalregisterwhichcanbeusedasastraightforwardstorageregister,abi-directionalshiftregister,anupcounterandadowncounter.Theregistercanbeloadedfromasetofparalleldatainputsandthemodeiscontrolledbya3-bitinput.The'termcnt'(terminalcount)outputgoeshighwhentheregistercontainszero.LIBRARYieee;USEieee.Std_logic_1164.ALL;USEieee.Std_logic_unsigned.ALL;ENTITYunicntrISGENERIC(n:Positive:=8);--sizeofcounter/shifterPORT(clock,serinl,serinr:INStd_logic;--serialinputsmode:INStd_logic_vector(2DOWNTO0);--modecontroldatain:INStd_logic_vector((n-1)DOWNTO0);--parallelinputsdataout:OUTStd_logic_vector((n-1)DOWNTO0);--paralleloutputstermcnt:OUTStd_logic);--terminalcountoutputENDunicntr;ARCHITECTUREv1OFunicntrISSIGNALint_reg:Std_logic_vector((n-1)DOWNTO0);BEGINmain_proc:PROCESSBEGINWAITUNTILrising_edge(clock);CASEmodeIS--resetWHEN000=int_reg=(OTHERS='0');--parallelloadWHEN001=int_reg=datain;--countupWHEN010=int_reg=int_reg+1;--countdownWHEN011=int_reg=int_reg-1;--shiftleftWHEN100=int_reg=int_reg((n-2)DOWNTO0)&serinl;--shiftrightWHEN101=int_reg=serinr&int_reg((n-1)DOWNTO1);--donothingWHENOTHERS=NULL;ENDCASE;ENDPROCESS;det_zero:PROCESS(int_reg)--detectswhencountis0BEGINtermcnt='1';FORiINint_reg'RangeLOOP h t t p : / / w w w . a m i . b o l t o n . a c . u k / c o u r s e w a r e / a d v e d a / v h d l / v h d l e x m p . h t m l ( 3 o f 6 7 ) [ 2 3 / 1 / 2 0 0 2 4 : 1 5 : 0 8 ](i)='1'THENtermcnt='0';EXIT;ENDIF;ENDLOOP;ENDPROCESS;--connectinternalregistertodataoutportdataout=int_reg;ENDv1;OctalD-TypeRegisterwith3-StateOutputsSimplemodelofanOctalD-typeregisterwiththree-stateoutputsusingtwoconcurrentstatements.LIBRARYieee;USEieee.std_logic_1164.ALL;ENTITYttl374I