清华大学数字集成电路作业三

2011-2012《数字VLSI》第三次课程作业1）下图为一个两输入的或非门，晶体管的尺寸如图所示，kn’=2kp’。表中为考虑静态时的情形，请将噪声容限按最小至最大排列。噪声容限最小的情形标为1，如噪声容限相同时可用同样的数字标注（请标注在表格右边的空列中。）图12)Atwo-stagebufferisusedtodriveametalwireof1cm.ThefirstinverterisofminimumsizewithaninputcapacitanceCi=10fFandaninternalpropagationdelaytp0=50psandloaddependentdelayof5ps/fF.Thewidthofthemetalwireis3.6μm.Thesheetresistanceofthemetalis0.08Ω/□,thecapacitancevalueis0.03fF/μm2andthefringingfieldcapacitanceis0.04fF/μm.a.Whatisthepropagationdelayofthemetalwire?b.Computetheoptimalsizeofthesecondinverter.Whatistheminimumdelaythroughthebuffer?c.Iftheinputtothefirstinverterhas25%chanceofmakinga0-to-1transition,andthewholechipisrunningat20MHzwitha2.5Vsupplyvoltage,thenwhat’sthepowerconsumedbythemetalwire?3)Toconnectaprocessortoanexternalmemoryanoff-chipconnectionisnecessary.Thecopperwireontheboardis15cmlongandactsasatransmissionlinewithacharacteristicimpedanceof100Ω.(SeeFigure2).Thememoryinputpinspresentaveryhighimpedancewhichcanbeconsideredinfinite.ThebusdriverisaCMOSinverterconsistingofverylargedevices:(50/0.25)fortheNMOSand(150/0.25)forthePMOS,whereallsizesareinμm.Theminimumsizedevice,(0.25/0.25)forNMOSand(0.75/0.25)forPMOS,hastheonresistance35kΩ.a.Determinethetimeittakesforachangeinthesignaltopropagatefromsourcetodestination(timeofflight).Thewireinductanceperunitlengthequals75*10-8H/m.b.Determinehowlongitwilltaketheoutputsignaltostaywithin10%ofitsfinalvalue.Youcanmodelthedriverasavoltagesourcewiththedrivingdeviceactingasaseriesresistance.Assumeasupplyandstepvoltageof2.5V.Hint:drawthelatticediagramforthetransmissionline.c.Resizethedimensionsofthedrivertominimizethetotaldelay.Figure2.Thedriver,theconnectingcopperwireandthememoryblockbeingaccessed.