ISSCC2016Visuals-T4-System-Level-Power-Management

ISSCC2016Tutorial4DigitalArchitecturesandSystemsSystemLevelPowerManagementTechniquesDavidFlynnFellow,ARMLtd,[e-mail],UniversityofSouthampton,UK30Nov2015DavidFlynnISSCC2016DASTutorial41of80OutlinePowerandEnergyPrinciplesandProcessTechnologyActivePowerManagementStandbyPowerManagementSystemLevelControlCaseStudy–SystemAggregatorCaseStudy–EmbeddedSensorDavidFlynnISSCC2016DASTutorial42of80CMOSPowerDissipationMinimizePstaticby:ReducingoperatingvoltageFewerleakingtransistorsReducingtransistorleakageMinimizePswitchby:LessswitchingactivityLoweroperatingvoltageReducedswitchingcapGoodsignalrise-timesTotalPowerDissipationActive,ClockedPowerDissipationUn-clockedPowerDissipationPtot=Pstatic+PswitchPstatic=(VddxIleak)Pswitch=fxαx((CeffxVdd2)+(tscxVddxIpeak))DavidFlynnISSCC2016DASTutorial43of80IleakIlscIswitchCMOSSwitchingPowerinDetailWhere:fistheclockfrequencyαistheactivityfactororprobabilityofanoutputtransitionCeffiseffectiveoutputcapacitancetheoutputdriverVddisdraintosourcesupplyvoltage(noteVdd2term)tscisthedurationofswitchingshortcircuitcurrentIpeakisthetotalinternalswitchingcurrentshortcircuitcurrentplusthecurrentrequiredtochargetheinternalcapacitancePswitch=fxαx((CeffxVdd2)+(tscxVddxIpeak))DavidFlynnISSCC2016DASTutorial44of80CMOSLeakagePowerinDetailSub-thresholdLeakage(ISUB):draintothesourcecurrentofatransistoroperatingintheweakinversionregion.GateLeakage(IGATE):gatecurrentthroughtheoxidetothesubstrate(gateoxidetunnelingandhotcarrierinjection)GateInducedDrainLeakage(IGIDL):draintothesubstratecurrentinducedbyahighfieldeffectintheMOSFETdrain(highVDG)ReverseBiasJunctionLeakage(IREV):currentflowcausedbyminoritycarrierdriftandgenerationofelectron/holepairsindepletionregions.Ileak≈ISUB+IGATE+IGIDL+IREVDavidFlynnISSCC2016DASTutorial45of80CMOSEnergyConsumptionEnergyistheintegralovertimeofpowerdissipatedActiveenergyincludesbothswitchingandunderlyingleakageIdleorStandbypowerisintegralofleakagepoweroverinactiveorsleeptimeTotalPowerDissipationDynamicPowerDissipationStaticPowerDissipationTotalEnergyConsumptionIdleEnergyDissipationEtot=(Pidle+Pactive)dt((fαCeffVdd2)+Eactive=(fαVddIsc)+(VddxIleak))dtEidle=(VddIleak)dt0t00tidletactiveActiveEnergyConsumptionDavidFlynnISSCC2016DASTutorial46of80PowerandEnergyinaNutshellPowerandEnergyconsumptiontrendsofaworkloadrunningatdifferentfrequencyandvoltagelevels.DFS:frequencyscalingonly,DVFS:frequency&voltagescalingFrequencyVoltageUsefulforDVSFrequencyPowerFrequencyEnergyDFSDFSDVFSDVFSf~(vdd-vt)/vdd1.3vt/vmax0.3P≈Cvdd2f+vddIleakAvg.power~heatE=∫PdtNeedDVFStosaveenergyBewareleakingforlonger!Reducingvoltagedoessaveenergyandextendbatterylife……butbewaretemperatureinversioneffectsandsofterrorsDavidFlynnISSCC2016DASTutorial47of80‘LP’and‘G’ProcessTechnologiesExampleofUMC65nmStandard(Generic)andLowLeakage(LP)TechnologynodeL65LL1P10ML65SP1P10MProcessLowLeakageStandardPerformanceLithography193nmDry193nmDryCoreVoltage(V)1.21.0(1.1VOverdrive)toxCore(A)1912IO(A)(IOVdd)30/52/65(1.8/2.5/3.3V)30/52/65(1.8/2.5/3.3V)PhysicalGateLength(nm)5540SalicideNiSiNiSiInterconnectCuCuInter/IntraMetalDielectricLowk(k=2.9)Lowk(k=2.9)1XMetalPitch(nm)2002006TSRAMCellSize(um2)0.5250.499DavidFlynnISSCC2016DASTutorial48of80DynamicandLeakagePower0510152025IntrinsicR.O.Delay(ps/stage)NormalizedIoff(pA/um)90SP1.0V90LL1.2V65SP1.0V65LL1.2V1101103102104105106PerformanceLeakagePowerNormalizedIoff(pA/um)IntrinsicRingOsc.delay(ps/stage)UMC65SP/LLDavidFlynnISSCC2016DASTutorial49of80“Silicon”Roadmap20102015202020252005WackinessSiliconEraSwitchesPatterningInterconnectMemory14nm10nm7nm5nm3.5nmFinFETLELESRAMSADPLELELEEUVHNWm-enhSAQP//3DICGraphenewire,CNTviaeNVMEUVLELEVNWOptoI/OEUV+DWEB2D:C,MoSEUV+DSAOptointspintronicsSeq.3DCuandWwiresLow-Cost(?)DavidFlynnISSCC2016DASTutorial410of80Section-2PowerandEnergyPrinciplesandProcessTechnologyActivePowerManagementStandbyPowerManagementSystemLevelControlCaseStudy–SystemAggregatorCaseStudy–EmbeddedSensorDavidFlynnISSCC2016DASTutorial411of80ActivePowerReductionClockGating(Micro-)Architecturalclockenablesand“instantiatedclockgates”(Common)ClockenabletermsandEDAclockgatinginferenceMultipleThreshold-Voltage,MultipleGate-LengthlibrariesDynamicFrequencyScaling(DFS)ReduceoperatingfrequencyifpossibleReducesaveragepower(butnottaskenergy),mayreduceheat(andleakage)Eliminatesbusy-waitingorpaddingwithNOPsDynamicVoltage&FrequencyScaling(DVFS)RequiresperformancepredictionDFSReducesvoltageiffrequencyisreducedReducestaskenergyBasedoncharacterizedfrequency–voltagepairs(lookuptable)AdaptiveVoltageScaling(AVS)ClosedloopoptimizationofVDDatrun-time(sensedfromSOC)Cansaveenergyevenatfixedfrequency(compensateProcess,Temperature)DavidFlynnISSCC2016DASTutorial412of80RTLandsynthesizableHDLsubsetsSynthesizableIPneedstobetechnologyindependentAndhighlyportableforsimulation,implementation,verificationHDLshavenoconceptofpower,assumesidealclocking“VDD”and“VSS”areimplicit/idealClocksaretreatedasideal,zerolatencyAddingMulti-VoltagesupporttoEDAtoolstookmanyyears