DC逻辑综合(DC课件整理)

DCRTLICICEDAICPVTDC112ASICDCDC=++HDLGTECHGTECHGTECHHDLDesignWare2).Port3).Clock4).Net5).Referenceget_designsget_cellsget_netsget_portsget_clocksall_inputsall_outputs(read_verilogdesign.v)(write–formatdb–outputdesign.db)121DFF1QDFF2DDDFF2setupDFF1DFF2DFF2DFF2holdEDASynopsysSynopsysDCDCSynopsysSysnopsys.libLC.dba)b)c)d)clkcreate_clock_period10get_portsclkset_dont_touch_networkget_portsclkNI/Oset_input_delay-max4–clockclkget_portsASreport_port-verbosereport_clockreset_designlist_libsremove_input_delayset_input_delayreport_libremove_designDCremove_from_collectionreport_port13create_clock–period10[get_portsclk]set_dont_touch_network[get_clocksclk]set_input_delay–max6–clockclk[all_inputs]remove_input_delay[get_portsclk]set_out_delay–max6–clockclk[all_outputs]set_driving_cellset_max_capacitanceload_ofcurrent_designmyblocklinksourcetiming_budgen.tcl#Assumeaweakdrivingbufferontheinputsset_driving_celllib_cellinv1a0[all_inputs]remove_driving_cell[get_portsclk]#limittheinputloadDCset_loadDCload_ofset_wire_load_modeenclosedreport_libsss_core_slowsetcurrent_designadd2set_wire_load_model–name160KGATESreset_designremove_design–designremove_design–alllist_fileslist_designslist_liblist_licenseshell1).2).3).create_clock(default)Rnet0RCDc=(Rnet/N)*(Cnet/N+Cpin)N=fanoutRCDc=Rnet*(Cnet+Cpins)4OperatingConditions1)2)3)4)report_path_groupreport_timing15EDA151create_clock–period[expr1.0/75*1000]–nameclkdcreate_clock–period10–nameclkecreate_clock–period20[get_portsclkc]set_dont_touch_network[get_clockclkc]current_designD_designsource–echo–verboseDconstraints.tcluniquifycompiledont_touchset_dont_touchD_desA_descurrent_designA_dessource–echo–verboseAconstraints.tclcompilecurrent_designD_desset_dont_touch[get_designsA_des]source–echo–verboseDconstraints.tclcompile16161group_path–nameinputs–from[all_inputs]group_path–nameoutputs–to[all_outputs]group_path–namecombo–from[all_inputs]–to[all_outputs]2nsgroup_path–nameclk1–critical_range0.3group_path–nameinputs–critical_range0.2group_path–nameoutputs–critical_range0.5current_designtopcharacterize–consU2current_designBwrite_script–oB_w.tclremove_design–hierBread_verilogB.vcurrent_designBlinksourceB_w.tclcompilewrite–hier–oB.dbcurrent_designtoplinkreport_constraintsDC-TCLTCLDCDC_SHELLdc_shellUNIXdc_transcriptmy_script.scrmy_script.tcldc_shellmy_script.scrdc_shell-tTCLmy_script.tclTCLDCTCLTCL$varnamevarname[commands]expr{}\”\””;”setheader_str“outputHeader”;#samelinecommentDC-TCL*”0-N”listsetcolors{redgreenblue}llengthlsort.setcolors[lsort$colors]foreachsetall_colors“redgreenblue”foreachcolor$all_colors{echo$colorisanicecolor………}Synopsystclcollectioncollectionget_*all_*collectionsetfoo[get_portsp*]sizeof_collection$foo;#fooquery_objects$foo;#foofilter_collectionfilter_collection[get_cell]“ref_name=~AN*”-filterget_cell*filter“dont_touch==true”==!====~!~TCLcheck_scriptdc_transcriptUNIXdc_shelldc_tclset/echohelpforeachllengthsizeof_collectioncollectionquery_objectsadd_to_collectionremove_from_collectionget_attributefilter_collectionpackagecheck_scriptmanprintvarclockTTAASYNCOREMID