The-Fundamentals-of-Digital-IC-Testing

By刘艾明200807苏州中科集成电路设计中心[e-mail]苏州工业园区集成电路人才公共实训基地苏州中科集成电路设计中心By刘艾明200807Page2Outline•Chapter1:IntroducttoTest---P3~P45Hardwareoverview…•Chapter2:BasicDCTests---P46~P110SIDD,DIDD,VIH/VIL,IIH/IIL…•Chapter3:FunctionalTests---P111~P153VIL/VIH,VOL/VOH…•Chapter4:DesignForTest---P154~P167StructuredDFT,SCAN,BIST,JTAG•Chapter5:Testertools---P168~P182Shmoo,PinMargin,Scope…苏州工业园区集成电路人才公共实训基地苏州中科集成电路设计中心By刘艾明200807Page3IntroducttoTestChapter1苏州工业园区集成电路人才公共实训基地苏州中科集成电路设计中心By刘艾明200807Page4WhyTestaDeviceDetectingFaults•FaultCoverage(faultgrading)isusedtodescribehoweffectiveavectorpatternisatdetectingandscreeningoutdevicesthatcontainFaults•Injecting“Stuck-At-Faults”(SAF)intocircuit•Simulatorprocessestheinputvectordatathroughthechipmodelandcapturestheoutputresponseofthemodel.苏州工业园区集成电路人才公共实训基地苏州中科集成电路设计中心By刘艾明200807Page5Stuck-At-FaultAnalysis苏州工业园区集成电路人才公共实训基地苏州中科集成电路设计中心By刘艾明200807Page6SimulationPattern苏州工业园区集成电路人才公共实训基地苏州中科集成电路设计中心By刘艾明200807Page7IntroducetoTestTheDUT:ThesemiconductordevicebeingtestedisoftencalledtheDUT(DeviceUnderTest).ItisalsosometimescalledaUUT(UnitUnderTest).TermsthatApplytotheDUT(signalpins)SignalPin:Input,output,Tri-stateandbi-directionalpins(powerandgroundpinsarenotincludedinthisdefinition).Signalpinshaveastructurewhichisdifferentfrompowerpins.InputPin:Adevicepinthatactsasabufferbetweenexternalsignalsandtheinternallogicofadevice.Theinputsensesthevoltageappliedtoitandtransmitsalogic0orlogic1leveltotheinternallogicofthedevice.苏州工业园区集成电路人才公共实训基地苏州中科集成电路设计中心By刘艾明200807Page8IntroducetoTestOutputPin:Adevicepinthatactsasabufferbetweentheinternallogicofadeviceandtheexternalenvironment.Anoutputpinprovidesthecorrectvoltagestoproducealogic0orlogic1levelandalsosuppliestheIOL/IOHcurrent.Three-stateOutput:Adevicepinthatfunctionsasanoutputpinandhastheaddedcapabilityofturningoff(goingtoahighimpedancestate)AlsocalledTri-stateoutput.Bi-directionalPin:Adevicepinthatfunctionsasaninput,anoutputandisalsocapableofturningoff(goingtoahighimpedancestate).苏州工业园区集成电路人才公共实训基地苏州中科集成电路设计中心By刘艾明200807Page9IntroducetoTestTermsthatApplytotheDUT(powerpins)PowerPin:Adevicepinthatisconnectedtoapowersupplybusorground.VDDandVCCaretypicalexamplesofpowerpins.VSSandgroundarealsoidentifiedaspowerpins.Powerpinshaveastructurethatisdifferentfromsignalpins.VCC:ThepowerpinthatsuppliesvoltageforaTTLdevice.VDD:ThepowerpinthatsuppliesvoltageforaCMOSdevice.VSS:ThepowerpinthatprovidesareturnpathforthepowersuppliedtotheVDDorVCCpin.Ground:ToconnectasignalpinorotherelectricalnodetothetestsystemreferencenodeortoVSS.Onadevicewithonlyonepowersupplyvoltage,VSSisoftencalled“ground.”苏州工业园区集成电路人才公共实训基地苏州中科集成电路设计中心By刘艾明200807Page10IntroducetoTestTestSystem:ThetestsystemisusedtosimulatetheoperatingconditionsthattheDUTwillexperienceasitisusedintheintendedapplication.ThetestsystemisoftenreferredtoasATEorAutomatedTestEquipment.TestProgram:ThepurposeofasemiconductortestprogramistocontrolthetesthardwareinamannerthatwillguaranteethattheDUTmeetsorexceedsallofitsdesignparametersDCTesting:Avoltageorcurrentismeasuredduringthetestandthepass/failresultsarebaseduponthemeasuredvalue.FunctionalTesting:Thedeviceactivelyperformslogicalfunctions.InputdataissuppliedtotheDUTandoutputdataiscomparedwiththeexpectedresults.苏州工业园区集成电路人才公共实训基地苏州中科集成电路设计中心By刘艾明200807Page11IntroducetoTestACtesting:ACtestingguaranteesthatthedevicecanperformitlogicalfunctionswithregardstotime.GrossTesting:Atestwithrelaxedconditions,withoutregardtothedevicespecificationparametervalues.苏州工业园区集成电路人才公共实训基地苏州中科集成电路设计中心By刘艾明200807Page12ElevatedTemperatureTestingTypicallyintherangeof70Cto100CProvidesmaximumstressWorstcaseenvironmentforhighfrequencytesting,thehotterthedietheslowertheoperationWorstcaseconditionforidentifyingpackagingdefects,liftedwirebondsetcElevatedatwafertest,packagetestorboth苏州工业园区集成电路人才公共实训基地苏州中科集成电路设计中心By刘艾明200807Page13BurnInStressingdevicewithelevatedtemperatureforanextendedperiodoftimeTemperaturesintherangeof70Cto125C4hoursto1000hoursAcceleratesinfantmortality(earlylife)failuresandpotentialreliabilityproblemsStaticBurn-in:Poweredup,quiescentLogicDynamicBurn-in:Poweredup,ActiveLogic苏州工业园区集成电路人才公共实训基地苏州中科集成电路设计中心By刘艾明200807Page14DeviceGuardbandingCanbeusedtoinsurealevelofsiliconquality.Keyparametersaretightenedbeyondthevaluesdefinedinthespecification.Example:adeviceisdesignedtooperateat100mHZ,executetestat110mHZ,thiswouldbea10%guardbandonfrequency.I/Olevels,currentsandACtimingsmaybeguardbanded.Guardbandlimitsdeterminedthroughcharacterization.GuardbandingreducesthepossibilityofshippingmarginaldevicesbymakingthetestprogrammoreRobust.苏州工业园区集成电路人才公共实训基地苏州中科集成电路设计中心By刘艾明200807Page15TestSystemGuardbandingInregardstohighspeeddigitaltest,itmaybenecessarytotakeintoconsiderationtheaccuracyofthetestsystemtiming.WhenthetimingspecificationsfortheDUTrequiresverypreciseedgeplacementsandthetestsystemisnotaccurateenoughtoguaranteethenecessaryprecision,itmaybeusefultorelaxthetestconditionstoaccountfortheinac