PowerCompiler-2010

1PowerCompilerSynopsysCustomerEducationServices© 2010Synopsys,Inc.AllRightsReservedSynopsys10-I-061-BSG-0072WorkshopGoalAcquirebasicskillstoanalyzeandoptimizeforpowerusingSynopsysPowerCompiler.3WorkshopPrerequisites UnderstandingofdigitalICdesign WorkingknowledgeofDesignCompiler KnowledgeofVerilogsimulation FamiliarwithLINUXenvironment4AgendaDAY1©2005Synopsys,Inc.AllRightsReservedSynopsys10-I-061-BSG-007Design-CompilerOverview2PowerAnalysis3PowerModeling1Gate-levelPowerOptimization4ClockGating55IconsUsedInThisWorkshopHint,tiporsuggestionAdditionalinformationCautionorwarning6AgendaDAY1©2005Synopsys,Inc.AllRightsReservedSynopsys10-I-061-BSG-007Design-CompilerOverview2PowerAnalysis3PowerModeling1Gate-levelPowerOptimization4ClockGating57UnitObjectivesAftercompletingthisunit,youshouldbeableto Recognizepowerinformationinlibrary Evaluatethequalityofalibrary Calculatepowermanuallyatgate-level8LowPowerMethodology Modeling: Theinfrastructureforpowermanagement LibrarymodelsforASICdesign Analysis: Providesvisibilityintopowerconsumption Requiredatalllevelsofabstraction Basedonscenariosimulation Optimization: Reducespowerconsumptionatalllevelsofabstraction9PowerModelCMOScellpowermodel Switchpower(dynamic): Chargingoutputload Internalpower(dynamic): Shortcircuit; Charginginternalload Leakagepower(static): StablestateInOutVddGndCloadInternalpower!=ShortCircuitPowerCloadPNVddIswIleakIshtGndOutCintPNVddIintswIshtGndIleakIn10CalculateCellPower SwitchPower: Dependentonoutputloadandinputtransition InternalPower: Pre-processedbycharacterizationtools Storedinlibrarypowerlookuptables SDPD(statedependentpathdependent) Leakagepower: Pre-processedbycharacterizationtools Storedinlibrary SD(statedependent)11library(power){time_unit:“1ns”voltage_unit:“1V”capacitive_load_unit(1,ff)nom_process:1.0;nom_temperature:25.0;nom_voltage:3.3;power_supply(){/*defaultis3.3*/default_power_rail:vdd;power_rail(vdda,3.3);power_rail(vddb,5.0);power_rail(gnd,0.0);}cell(cell1){pin(A,B){direction:inputcapacitance:1.0}pin(Z){direction:outputcapacitance:1.0output_signal_level:vddb.......SwitchingPowerRelatedInfoInLibrary UnitofC,V The“nom_voltage”usedasdefaultvoltage “power_supply”definesmultiplevoltagesusedinthelibrary Inputpincapacitanceispartofthedrivingcell’soutputload “output_signal_level”specifiesvoltageusedforcomputingswitchingpower12 cell(FF1){ area:2.0; cell_leakage_power:1.0; ... pin(q){ …... internal_power(){ rise_power(load_trans){ values(“1.0,1.5,2.0,2.1,2.5”\ “2.5,3.0,3.5,4.0,4.5”\ “2.7,4.0,4.1,5.0,5.3”);}related_pin:clk;when:j&k;} pin(clk){ …... internal_power(){ rise_power(trans_time){ values(“0.55,0.6,0.7”); } } .........InternalPowerInLibraryTemplatesInternalPowerTableslibrary(power){........voltage_unit:“1V”capacitive_load_unit(1,pf);........power_lut_template(load_trans){variable_1:total_output_net_capacitance;variable_2:input_transition_time;index_1(“0.1,5.0,6.0”);index_2(“0.1,3.0,7.0,15.0,20.0”);}power_lut_template(load_only){variable_1:total_output_net_capacitance;index_1(“0.0,5.0,10.0”);}power_lut_template(trans_time){variable_1:input_transition_time;index_1(“0.0,3.0,20.0”);}Unit13LeakagePowerInLibrarylibrary(power){......leakage_power_unit:1pW;default_cell_leakage_power:0.2;k_volt_cell_leakage_power:0.23;k_temp_cell_leakage_power:0.32;k_process_cell_leakage_power:0.35;.......cell(AN2){area:2.0;cell_leakage_power:0.5678;leakage_power(){when:!A&!B;value:0.0175811;}leakage_power(){when:!A&B;value:0.0184178;}}}14PowerLevelForMultiVddCellM-VddCellVdd1Vdd2pin(Y){internal_power(){power_level:VDD1;power(power_rl){values(1.934150,2.148130);}}internal_power(){power_level:VDD2;power(power_rl){values(1.032871,0.823947);cell(mycell){leakage_power(){power_levelVDD1;value:3.459;}leakage_power(){power_levelVDD2;value:6.332;}leakage_power(){power_levelVDD1;when:!A1A2;value:4.792;}leakage_power(){power_levelVDD2;when:“!A1A2;value:5.176;}StatesmustbeidenticalfordifferentrailsDefaultleakage15ToggleRateBasedAveragePowerAnalysisCell4toggles40nsTr=4/40=0.1(GHz)P(dyn)=E(dyn)/time=E(toggle)*4/40=E(toggle)*Tr DigitalcircuitconsumesdynamicenergyE(toggle)foreachtoggle 4togglesconsumesenergyE(dyn)=E(toggle)*4 Togglerate(Tr)isToggles/time DynamicpowerequalstoenergytimestogglerateP(dyn)=E(toggle)*Tr Poweranalysisneedstoggleoneverynode16ToggleRateBasedPowerAnalysisExampleTakeaninverterforexampleInternalpower=(Erise+Efall)*0.5*Tr=(0.214947+0.094129)x.5x.02e9=3.09076uwSwitchingpower=cv2*Tr*0.5=0.27x3.32x0.02e9x0.5=29.403uwDynamicpower=PInternal+Pswitching=3.09076+29.403=32.494uw0.27pfTr=0.02(GHz)ramp=1.2nspower_lut_template(pwarc_rl_1){variable_1:input_transition_time;variable_2:total_output_net_capacitance;index_1(0.40000,1.20000,2.80000,4.20000);index_2(0.04000,0.13000,0.27000,0.41000,);}internal_power(){rise_power(pwarc_rl_1){values(0.15375,0.13449,0.12584,0.12271,\0.33069,0.26098,0.214947,0.1920,\0.74832,0.60830,0.49841,0.43109,\1.12893,0.95332,0.79195,0.69608,\}fall_power(pwarc_rl_1){values(0.04088,0.02297,0.0144,0.0122