多通道高密度的TDC@FPGA主要指标时间测量精度-Indico@IHEP

高精度时间测量2011年研究进展核探测与核电子学国家重点实验室（筹）中国科学技术大学近代物理系刘树彬Page2UniversityofScienceandTechnologyofChina主要内容基于进位延时单元内插的TDC@FPGA•10ps高精度TDC@FPGAIP基于TDC@FPGA的通用模块•16通道100psTDC@FPGA通用插件•高密度高精度时间测量插件基于ACTEL的TDC@FPGA高精度时间测量技术的应用Page3UniversityofScienceandTechnologyofChina基于进位延时链的TDC@FPGA工作原理CoarseCounter(CoarseTime)+TimeInterpolationwithinoneclockperiod(FineTime)CLKHitInCNTNN+1QQSETCLRDQQSETCLRDQQSETCLRDQQSETCLRDEncoderUnitFIFOCLKHitStep[0]Step[1]Step[2]Step[n-1]EnableCLKLatchDoubleCoarseTimeCountersCoarseTimeSelectorCLKFineTimeControlChannelIDTemperatureReadRdClkOutDataEmptyFullDelayDelayDelayDelayDelay(a)(b)Page4UniversityofScienceandTechnologyofChina时间内插技术在FPGA中的实现方法采用FPGA内的进位延时单元实现内插AdderAdderAdderCi=0Sum[0]Sum[1]Sum[n-1]Hit1Co[0]Co[1]Co[n-2]Co[n-1]1100SwitchMatrixSLICE(0)XmYnSLICE(2)XmYn+1SLICE(1)Xm+1YnSLICE(3)Xm+1Yn+1InterconnecttoNeighborsSLICEMSLICELCLBCINCINCOUTCOUTSLICEX65Y100SLICEX65Y101SLICEX65Y102SLICEX65Y103b)Carrychainofamulti-bitaddera)Carry-ininaSlicec)RoutinaSLICEPage5UniversityofScienceandTechnologyofChina基于FPGA进位单元的TDC研究进展2005年：~100psBinSize,50psRMS;TNSVol.53,Issue1,Part2国际上第一次采用进位延时单元实现时间内插2009年：~50psBinSize,20psRMS;TNSVol.57,Issue2,Part1时间测量性能修正算法：自校准，温度和电压变化补偿2011年：~10psBinSize(Effective),10psRMSTNSVol.58,Issue4,Part2基于吴进远的WaveUnionTDC，进行了深入分析和改进Page6UniversityofScienceandTechnologyofChina1:Unleash1212Device:EP2C8T144C6PlainTDC:Max.binwidth:160ps.Averagebinwidth:60ps.WaveUnionTDCA:Max.binwidth:65ps.Averagebinwidth:30ps.0204060801001201401601800163248648096112128binwidth(ps)PlainTDCWaveUnionTDCAWaveUnionTDCbyJ.WuPage7UniversityofScienceandTechnologyofChinaWaveUnionTDC国内外现状德国GSI:WaveUnionTypeA:10psRMSIEEETNSVol.58,Issue4,Part1,pp.1547-1552清华:WaveUnionTypeA:～20psRMSIEEENSS/MIC2010,pp.396-399高能所：科大:WaveUnionTypeB:10psRMSIEEETNSVol.58,Issue4,Part2,pp.2011-2018Page8UniversityofScienceandTechnologyofChinaDelay10Hit123kk+1n-1nINVHit_InDelayDelayDelayDelayQQSETCLRDQQSETCLRDQQSETCLRDQQSETCLRDQQSETCLRDQQSETCLRDQQSETCLRDCLKEncoderStep[1]Step[2]Step[3]Step[k]Step[k+1]Step[n-1]Step[n]OSC_InvMUXNDelaySelectorSELINV+Delay+MUXWaveUnionLauncher10-psTDC@FPGA工作原理Page9UniversityofScienceandTechnologyofChina10-psFPGATDC的主要特性WaveUnionLauncher内嵌在进位链，不占用额外资源无限振荡次数(N)BinSize,RMSv.s.N主要技术指标•9独立通道，~60%逻辑资源(XC4VFX60)•24Bits粗计数，~168ms动态范围•10psRMS,Binsize~10ps(N=4)Page10UniversityofScienceandTechnologyofChinaCLKTOSCTOSCT1t2tNtCLKHitOsc.3t123456789101112131415161718192021222324050100150200NTDCBinABC10-psTDC@FPGA的数据处理tNtttkttttttttttNNkk)1(...)1(...200303202101CLKOSCTTtNtimesOscillationN1ii00tN1tPage11UniversityofScienceandTechnologyofChinaRMStimingprecision(σdelay)vs.N，误差主要来自：•Non-uniformeddistributionofthecarrychaindelay(σcell)•Randomuncertaintyoftheoscillationperiod(σosc)•Othercontributors,e.g.thesteadyoftheclock(σother)Threepossiblecases:•Case1:σoscσcell•Case2:σosc≈σcellThebesttiming@•Case3:σoscσcell2other2cell2oscdelayN141NcelldelayN1osccell2Noscdelay21N10-psTDC的时间测量分析Page12UniversityofScienceandTechnologyofChina48121620242832324681012141618NRMS(ps)test80100120140160180200020040060080010001200TimeInterval(ps)CountRMS:8ps时间测量精度仿真和测试的比较Test:RMSvs.N14812162001020304050607080NRMS(ps)σ=0psσ=10psσ=30psCase1:σoscσcellCase2:σosc≈σcellCase3:σoscσcell321Simulation:RMSvs.NActualimplementationfallsintoCase2(a)(b)(c)Page13UniversityofScienceandTechnologyofChina10-psTDC@FPGA应用考虑ProsandCons√LargerNresultsinsmallerbinsize,lowertimingprecision×LargerNresultsinlargerdeadtime~(N+1)*TCLK,200250300350400450500050010001500200025003000TimeInerval(ps)CountABFitofAFitofBBA200225250275300325350375400425450475500500050010001500TimeInterval(ps)CountABFitofAFitofBBANoAveragingN=4B:~325psA:~350psPage14UniversityofScienceandTechnologyofChina主要内容基于进位延时单元内插的TDC@FPGA•10ps高精度TDC@FPGAIP基于TDC@FPGA的通用模块•16通道100psTDC@FPGA通用插件•高密度高精度时间测量插件基于ACTEL的TDC@FPGA高精度时间测量技术的应用Page15UniversityofScienceandTechnologyofChina基于FPGA的高性能时间测量插件研制~50psRMS,100psBin•NIM,USB,otherplatforms•16Channels,~170msDynamicrange•single-endedinput,Rangefrom-5V~5V,withon-boardfastdiscriminatorPage16UniversityofScienceandTechnologyofChina80100120140160180200020040060080010001200TimeInterval(ps)CountRMS:8psTDCLogicIPDesign,+TriggerMatching•~170msDynamicrange•LVDSinput•9ChannelsinXC4VFX60,•~20psRMS,50psBincostlessthan20%ofthetotallogicelements(total50kLUTsandRegistersavailableinXC4VFX60)•10psRMS,12psBin,cost60%ofthetotallogicelements基于FPGA的高性能时间测量插件研制温度补偿Page17UniversityofScienceandTechnologyofChinaTDC@Virtex5FPGA通用高性能插件(PXI,VME)•~25psRMS,30psBin•~170msDynamicrange•LVDSinput,16channels,onPXI,VME•TriggerMatching55060065070075080085090001000200030004000500060007000Delay(ps)CountRMS:14psRMS:14ps基于FPGA的高性能时间测量插件研制Page18UniversityofScienceandTechnologyofChina55060065070075080085090001000200030004000500060007000Delay(ps)CountRMS:14psTDC@FPGAPXIModuleTDC@FPGATestSetupRMS:14psUSTC基于FPGA的高性能通用时间测量插件TDC@FPGAVMEModulePage19UniversityofScienceandTechnologyofChina多通道高密度TDC@FPGA较高的集成度•单板单FPGA实现64个TDC通道粗-细结合的