组合逻辑电路(加法器)

加法器1、半加器半加器和全加器能对两个1位二进制数进行相加而求得和及进位的逻辑电路称为半加器.半加器真值表AiBiSiCi0001101100101001iiiiiiiiiiBACBABABAS=1&AiBiSiCiAiBiSiCi∑CO半加器符号半加器电路图加数本位的和向高位的进位2、全加器能对两个1位二进制数进行相加并考虑低位来的进位，即相当于3个1位二进制数相加，求得和及进位的逻辑电路称为全加器。AiBiCi-1SiCi0000010100111001011101110010100110010111AiBiCi-1000111100010111010Si的卡诺图AiBiCi-1000111100001010111Ci的卡诺图17421iiiiCBAmmmmSiiiiiiiiBACBABAmmC153)(Ai、Bi：加数，Ci-1：低位来的进位，Si：本位的和，Ci：向高位的进位。iiiiiiiiiiiiiiiiiiiiiiBACBABACBABABACBACBABAmmC111153)()(全加器的逻辑图和逻辑符号=1&&AiBiCi-1SiCi(a)逻辑图(c)国标符号AiBiCi-1SiCiAiBiCi-1SiCi(b)曾用符号CICO∑&FA=1111111111117421)()()()(iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiCBACBACBACBCBACBCBACBACBACBACBAmmmmS11iiiiiiiCBCABAC用与门和或门实现1111iiiiiiiiiiiiiCBACBACBACBASSiCi111AiBiCi-1&&&&&&&&&用与或非门实现AiBiCi-1000111100010111010Si的卡诺图AiBiCi-1000111100001010111Ci的卡诺图1111iiiiiiiiiiiiiCBACBACBACBAS11iiiiiiiCBCABAC先求Si和Ci。为此，合并值为0的最小项。再取反，得：1111iiiiiiiiiiiiiiCBACBACBACBASS11iiiiiiiiCBCABACCCiSi&≥1&≥1AiBiCi-11111111iiiiiiiiiiiiiCBACBACBACBAS11iiiiiiiCBCABAC实现多位二进制数相加的电路称为加法器。1、串行进位加法器加法器构成：把n位全加器串联起来，低位全加器的进位输出连接到相邻的高位全加器的进位输入。C3S3C2S2C1S1C0S0C0-1A3B3A2B2A1B1A0B0∑COCICOCI∑∑∑COCICOCICICICICICICICICI特点：进位信号是由低位向高位逐级传递的，速度不高。2、并行进位加法器（超前进位加法器）iiiBAGiiiBAP进位生成项进位传递条件11)(iiiiiiiiiCPGCBABAC进位表达式1001230123123233233323310012012122122212210010110111011100001000CPPPPGPPPGPPGPGCPGCCPSCPPPGPPGPGCPGCCPSCPPGPGCPGCCPSCPGCCPS11iiiiiiCPCBAS和表达式4位超前进位加法器递推公式S0S1S2S3C3C0-1A0B0A1B1A2B2A3B3=1&&≥1P0G0P1G1P2G2P3G3≥1≥1=1&&&&=1&&&C0C1C2≥1&&=1=1=1=1&=1&&超前进位发生器16151413121110974LS28312345678VCCB2A2S2B3A3S3C3TTL加法器74LS283引脚图161514131211109400812345678VDDB3C3S3S2S1S0C0-1CMOS加法器4008引脚图A3B2A2B1A1B0A0VSSS1B1A1S0B0A0C0-1GNDA15~A12B15~B12A11~A8B11~B8A7~A4B7~B4A3~A0B3~B0S15S14S13S12S11S10S9S8S7S6S5S4S3S2S1S04位加法器4位加法器4位加法器4位加法器C15C11C7C3C0-1加法器的级连集成二进制4位超前进位加法器加法器的应用1、8421BCD码转换为余3码BCD码0011余3码S3S2S1S0C3C0-1A3A2A1A0B3B2B1B0S3S2S1S0C3C0-1A3A2A1A0B3B2B1B0=1=1=1=1被加数/被减数加数/减数加减控制BCD码+0011=余3码2、二进制并行加法/减法器C0-1＝0时，B0=B，电路执行A+B运算；当C0-1＝1时，B1=B，电路执行A－B=A+B运算。3、二-十进制加法器C&进位输出被加数加数“0”1&&8421BCD输出S3'S2'S1'S0'C34位二进制加法器C0-1A3A2A1A0B3B2B1B0S3S2S1S0C34位二进制加法器C0-1A3A2A1A0B3B2B1B0进位输入13233SSSSCC修正条件