Verilog操作AD9833

moduleDDS(inputrst_n,inputclk,outputdds_sclk,outputdds_sdatasin1,outputdds_sdatasin2,outputdds_fsync);reg[15:0]configwordsin1[4:0];reg[15:0]configwordsin2[4:0];parameterOneSecond=30'd20000000;//fpgasendconfigurationbyteto9833atabout2secondafterfpgaisresetreg[29:0]clkcounter;regsecondflag;//onesecondcounteralways@(posedgeclkornegedgerst_n)beginif(!rst_n)beginsecondflag=0;clkcounter=26'd0;endelseif(clkcounter==OneSecond)beginsecondflag=1'b1;endelsebeginclkcounter=clkcounter+1'b1;endend//2.5MHzcounterregdds_sclk;reg[3:0]sclkcounter;always@(posedgeclkornegedgerst_n)beginif(!rst_n)begindds_sclk=1'b1;sclkcounter=4'b0;endelseif(sclkcounter==5)begindds_sclk=1'b0;sclkcounter=sclkcounter+1'b1;endelseif(sclkcounter==10)begindds_sclk=1'b1;sclkcounter=0;endelseif(secondflag==1'b1&&!sendfinish)//runsclkcounterbetweensecondturnsto1andsendfinishturnsto0//elseif(secondflag==1'b1)//runsclkcounterbetweensecondturnsto1andsendfinishturnsto0sclkcounter=sclkcounter+1'b1;endalways@(posedgeclkornegedgerst_n)//为了延长发送时钟周期，将DDS的基频改成了10Mbeginif(!rst_n)beginconfigwordsin1[0]=16'b0010_0001_0000_0000;configwordsin1[1]=16'b0101_1000_1001_0011;//10KHz1000001100010010011configwordsin1[2]=16'b0100_0000_0001_0000;configwordsin1[3]=16'b1100_0000_0000_0000;configwordsin1[4]=16'b0010_0000_0000_0000;configwordsin2[0]=16'b0010_0001_0000_0000;configwordsin2[1]=16'b0111_0001_0010_0110;//20KHz10000011000100100110configwordsin2[2]=16'b0100_0000_0010_0000;configwordsin2[3]=16'b1100_0000_0000_0000;configwordsin2[4]=16'b0010_0000_0000_0000;endendregdds_fsync;always@(posedgeclkornegedgerst_n)beginif(!rst_n)dds_fsync=1'b1;elseif(sendfinish)dds_fsync=1'b1;elseif(secondflag==1'b1)dds_fsync=1'b0;endreg[4:0]bitcounter;reg[2:0]wordcounter;regsendfinish;regdds_sdatasin1;regdds_sdatasin2;reg[15:0]tempwordsin1;reg[15:0]tempwordsin2;always@(posedgeclkornegedgerst_n)beginif(!rst_n)beginsendfinish=1'b0;bitcounter=0;wordcounter=0;tempwordsin1=configwordsin1[0];tempwordsin2=configwordsin2[0];endelseif(wordcounter==4)if(bitcounter==15)beginif(sclkcounter==1)begindds_sdatasin1=tempwordsin1[15];dds_sdatasin2=tempwordsin2[15];endif(sclkcounter==9)beginsendfinish=1'b1;wordcounter=0;bitcounter=0;endendelsebeginif(sclkcounter==1)begindds_sdatasin1=tempwordsin1[15];dds_sdatasin2=tempwordsin2[15];endif(sclkcounter==9)beginbitcounter=bitcounter+1'b1;tempwordsin1=tempwordsin11;tempwordsin2=tempwordsin21;endendelseif(bitcounter==15)beginif(sclkcounter==1)begindds_sdatasin1=tempwordsin1[15];dds_sdatasin2=tempwordsin2[15];endif(sclkcounter==9)beginbitcounter=0;wordcounter=wordcounter+1'b1;tempwordsin1=configwordsin1[wordcounter+1];tempwordsin2=configwordsin2[wordcounter+1];endendelsebeginif(sclkcounter==1)begindds_sdatasin1=tempwordsin1[15];dds_sdatasin2=tempwordsin2[15];endif(sclkcounter==9)beginbitcounter=bitcounter+1'b1;tempwordsin1=tempwordsin11;tempwordsin2=tempwordsin21;endendendila_0ad_ila(.clk(clk),//inputwireclk25MHz.probe0(dds_sclk),//inputwire[0:0]probe0.probe1(dds_sdatasin1),//inputwire[0:0]probe1.probe2(dds_sdatasin2),//inputwire[0:0]probe2.probe3(dds_fsync),//inputwire[0:0]probe3.probe4(1),//inputwire[3:0]probe4.probe5(1),//inputwire[3:0]probe5.probe6(1),//inputwire[3:0]probe6.probe7(1),//inputwire[7:0]probe7.probe8(1),//inputwire[7:0]probe8.probe9(1),.probe10(1));endmodule