DDR存储器的测试方法研究及实现

上海交通大学硕士学位论文DDR存储器的测试方法研究及实现姓名：王剑申请学位级别：硕士专业：计算机技术指导教师：刘胜利;朱鲁华20040901DDR1DDRSDRAMDualDateRateSDRSMRambusDDRDDRDDRETS770DDRDDRDDRDDRDDRDDRETS770DDRDDRVLSIDDR2DDRSDRAMDDRDDRDDRSDRAMDDRSDRAMDDRSDRAMDDRDDRDDR3RESEARCHONDDRMEMORYTESTMETHODSANDIMPLEMENTATIONABSTRACTDDR(alsocalledtheDualDateRateSDRAM)isahigh-speedCMOSanddynamicrandomaccessmemory.DDRmemoryrepresentsanewdirectionofthememorydevelopmentthatwillcontendwithRambusinthefuture.Tocomparewiththegeneralsynchronousdynamicrandommemory(SDRAM)DDRcanreaddatafromtherisingandfallingedgesofaclockpulse.ThereforethedatatransmissionrateofDDRdoublesthatoftheclockfrequencyanditsoperatingfrequencyismuchhigher.Startingwithanintroductiononthedevelopmentsandcategoriesofmemorytechnologiesthispapermakesasystematicdescriptionontheperformanceindexesfailuremodesandbasictestapproachesformemories.ItputsforwardseveralDDRtestapproachesrespectivelybasedonboard-levelspecialmemorytestingsystemandETS770logictestingsystemfordifferentlevelsofDDRtest.TheDDRtestapproachbasedonboardlevelismainlyusedinthedesignphasewhichexamsandteststheDDRinterfacedrivethecontrolsignalandthehigh-speedworksandwhatitmostconcernsaboutisthepracticalperformanceoftheinstruments.Thewrite-readmodeoftheDDRmemoryisdifferentfromothermemorieswhichhasahigheroperationalspeedandrequiresmoreindesignandusesoitisquitenecessarytocarryouttheboardleveltestandensuringthenormaluseoftheinstruments.TheproposingandimplementationofthisapproachwillsolvemanyproblemsintheDDRengineeringapplication.FortheapproachbasedonspecialmemorytestDDR4systemmainlyaimsatproduct-manufacturinganduseracceptancewhichcarriesoutcomprehensivetestonthefunctionsandAC-DCparametersoftheinstruments.TheDDRtestapproachbasedonETS770logictestsystemisorientedtowardsuseracceptanceandreliabilitytest.DDRmemoryhassomespecialfeatures.Atpresenttherearenospecial-purposeDDRSDRAMtestsystemsdevelopedinChina.Exceptsomemanufacturersfewresearchorganizationshavepurchasedspecial-purposeDDRSDRAMtestsystemsfromabroadsincethesesystemsareveryexpensive.ThereforethedomesticusersaregreatlylimitedintheacceptanceofDDRSDRAMandtheresearchofreliabilitytest.Thissubjectusesamicrocomputerforprogrammingandachievestheautomaticgenerationoftestvectorswithoutthesupportofspecial-purposememorytestpatterngenerator.AftermakingautomatictransitionandmanualmodificationofthesetestvectorswesuccessfullyimplementedthetestonseveralmemorypattersofDDRSDRAM.TheinnovationofthissubjectliesinthatitissuccessfullyimplementedonthelogicverificationsystemsbytakingfulladvantageofthecharacteristicsofDDRSDRAMandcombiningtheautomaticgenerationoftestvectorswiththetestpatternsofmemory.TocarryoutresearchesfortheDDRmemorytestapproachondifferentlevelswilldohelptotheDDRmemorytestforuserswhichhasprettyhighpracticalvalues.KEYWORDSmemoryDDRSDRAMtestmethodtestvectorsETS770TestSystem1200410152DDR7217ìm0.25ìmm50nm81220151618DDR8DDR91.2DDR10DDR11DDR12DDR13DDR14DDR152.1.1DDR16DDR17DDR18SDRAMSynchronousDRAM2.1.2DDR19S=2nn=log2StAtMtMtAtMmMmtWB=DDR20WwMmtWB=Mm∑ΡsΣΡ=Ρ∑=niirt1i∑==niirtnRT11iDDR21∑=niimt1∑==niimtnmT11∑∑∑===+=+=niniiiniimtrtrtmTRTRTA111DDR222.2.1DDR23DDR242.2.2DDR252.3.1DDR26DDR272.3.2DDR282ìmBBDDR29DDRDDRSDRAMDualDateRateSDRSMDDRSDRAM133MHz2.128GB/sDDR3.3VLVTTL2.5VSSTL2SDRAMSDRAMRambusDDRRambusMT46V32M16DDR512MbDDRMT46V32M16DDRMT46V32M1613103-1DDR32Megx16DDR30MT46V32M16VDD=+2.5V±0.2VVDDQ=+2.5V±0.2VDDR31DDRSDRAMSSTLCLASSTTLCMOSDQSDQsDQSDDRSDRAMDQsDQs400MHzDDRDDRDDR3.2.1DDRSDRAMDDR32FPGA3-33-23-3FPGADDR33FPGACLK_DCMDDRSDRAMDDR_CONTDDRSDRAMDDR_STI(DDR_RCV)HSTL(HSTL_SENDHSTL_RCV)SSTL(SSTL_FEEDBACK)FPGAJTAGPC_DEBUG1CLK_DCM100M200MDDRSDRAM2DDRSDRAM(DDR_CONT)(DDR_STI)DDRSDRAM3-43-5DDRSDRAMDDR34DDRSDRAMØ80SSTL2-CLASS2212Ø/22641312RegisterØ2ZDBDDRSDRAMA(DDR_STI)RAMRAMDDR_CONT3-6DDRSDRAMDDR35B(DDR_RCV)DDRSDRAMRAMRAM4SSTLSSTLFPGA5HSTL3-7DDRSDRAM3-8DDRSDRAMDDR36HSTLFPGABhstl_rcv6FPGAFPGAPROMFPGAAJTAG3-9HSTLDDR37BPC_DEBUG3-10FPGA3-11DDRSDRAM3-12DDRSDRAMDDR383.2.2FPGARegister/13264FPGADDRDDRDDR3.2.3100MFPGA200M3.3V2.6V/2.5V1.5VFPGA1.5VHSTL1.25V0.75V3.3V2.5V1.25V1.5V0.75VDDR393.2.4DDRDDRDDR1FPGADQSDQSDQsFPGADDRDDRRAMRAMDDR403.3.1NNMNRAM01Scan11003-13ab10DDR411001R0W1ROW13-15c3-15d10R1W001013-15bRAMDDR42102-400110RAM103-16a001101103-16a01110DDR433-16b013-16b1013.3.2N2N2N2N²A0A0R0A0A0DDR44A0A1A2AnR0R0R0R0R0R0W1R1R1R10R0R0R0R01R1R1R11R0R0R0R01R1R1R1R0R0R0R01R1R1R10R0R0R0R0R0R0A0A0W1A1R0A0R1A1A2DDR45A0A0R1A2A3R0A0R1A3A4A0W0A1A1W1A2R0R0R0R0R1R1R10R0R01R1R1R10R0R01R1R1R10R0R01R1R1R10R0R0R0A0W1A1R0R1A2R0A0R1A3R0R0DDR46A0R1A13.3.3N3/2N3/2N2N2N2N3/2DDR47DDR48DDR493.3.4N1og2NN1og2Nº¹0A000DDR50DDR513.3.4MT46V32M16N2N3/2N1og2NDDR523.4DDR3.4.13-25TP3-25()HCTPTPHCTPHCDDR53LSI(ALPG)(SQPG)MPUMCUAISC4I/OI/O10I/0(256)DCDC(PMU)(DPS)6VLSIDDR543.4.23-26CPU(TDM)3-26DDR55(1)CPUCPU(2)ECLRAM|//(3)AxAyAzAyAzDDR56n2nnRAM/RAMAxAyAz(4)416(TDM)RAMTDMnnnROMROMCPUROMTDMROMnTDMnCPUDDR57(1)(2)3-27(D1D2)(D3)D1D2D1D2(D1xD1yD2xD2yD3D11DD2+1-11DDR583-27(3)CP60CP7CP61D1D2D1xD1y010D101110(4)/CP60/CP61/DDR593.4.3(DBM)DBMVLSI(1)(DBM)DBMDBM(DBMDATA)DBM(DBMCARE)DBM(DBMSCM)BMA(2)VLSIDBMEC