(集电)TD-LO18-DR-2001v8P

SemiconductorManufacturingInternationalCorporationDoc.No.:TD-LO18-DR-2001Doc.Title:0.18umLogic1P6MSalicide1.8V/3.3VDesignRuleDoc.Rev:8PTechDevRev:2.0PageNo.:1/5959TheinformationcontainedhereinistheexclusivepropertyofSMIC,andshallnotbedistributed,reproduced,ordisclosedinwholeorinpartwithoutpriorwrittenpermissionofSMIC.Accordingto:SMICDocumentControlProcedure;AttachmentNo.:QR-QUSM-02-2001-023;Rev.:12008-06-27DocumentLevel:(ForEngineering&QualityDocument/工程暨品质文件专用)Level1-ManualLevel2–Procedure/SPEC/ReportLevel3-OperationInstructionSecurityLevel:Security1-SMICConfidentialSecurity2-SMICRestrictedSecurity3-SMICInternalDocumentChangeHistoryDoc.Rev.TechDev.Rev.EffectiveDateAuthorChangeDescription0T2001-12-24AllenFan范忠黎Initiate1T2002-3-7FengGuangTaoInthisnewversion1T,theterminologyisuniformed.Andanumberofverbaldescriptionerrorsandfigureerrorsinpreviousversionarealsocorrected.1.1T1.02003-06-10JianHua_JuAddTechnologyDevelopRevision:1.02T2.02003-12-09Stella_Huang1)DeleteESD2layer2)Addmasklayerdigitizedareadescription3)Addnwellresistorruledescription4)Addnativedevicerule5)ModifyGT.10,GT.11,GT.126)AddGT.14rule7)AddGTdensityrecommendation.8)Addpolyresistorrulerecommendation1.8g9)AddNLL.14,PLL.14,NLH.14,PLH.14rule10)ModifymetaldummyruledescriptionM1.8,Mn.8,MT.73P2.02007-01-25MatthewShenAddMn.9ruletopreventBEOLcrackissueReplaceFab/E1withPIEfororg.namechange4P2.02007-07-31XiaoliangTangAddguidelineforpolyimidelayoutminima,addtherelatedRULENO.;DESCRIPTION;LAYOUTGUIDELINE5P2.02009-11-13AmyLin1)Update0-PartI:DescriptionofSMICMaskLayers2)Add2.4Recommendedmetalslotrules.6P2.02010-11-02ChandlerRen1)Updateitem7PartIISuggestionfortheoptimizationofcircuitdesignaddAvoidbigmetallinestack=3layers,Avoidsmallspacebetweenbigmetallines.Avoidsmallspacebetweendenseviaarray;2)Updateitem7.1.19Metalrule,deleteMn.9toaddMn.10,Mn11,Mn.12;SemiconductorManufacturingInternationalCorporationDoc.No.:TD-LO18-DR-2001Doc.Title:0.18umLogic1P6MSalicide1.8V/3.3VDesignRuleDoc.Rev:8PTechDevRev:2.0PageNo.:2/5959TheinformationcontainedhereinistheexclusivepropertyofSMIC,andshallnotbedistributed,reproduced,ordisclosedinwholeorinpartwithoutpriorwrittenpermissionofSMIC.Accordingto:SMICDocumentControlProcedure;AttachmentNo.:QR-QUSM-02-2001-023;Rev.:12008-06-277P2.02010-11-26ChandlerRenUpdateitem7.1.19Metalrule,modifyMn.10,Mn11,Mn12;ThisisforIMDcrackissuetooptimizeMetalrule，add1.23BondPadOpeningDesignRuleSemiconductorManufacturingInternationalCorporationDoc.No.:TD-LO18-DR-2001Doc.Title:0.18umLogic1P6MSalicide1.8V/3.3VDesignRuleDoc.Rev:8PTechDevRev:2.0PageNo.:3/5959TheinformationcontainedhereinistheexclusivepropertyofSMIC,andshallnotbedistributed,reproduced,ordisclosedinwholeorinpartwithoutpriorwrittenpermissionofSMIC.Accordingto:SMICDocumentControlProcedure;AttachmentNo.:QR-QUSM-02-2001-023;Rev.:12008-06-278P2.02012-01-10JennyPang1.1.6DG:changeDG.4ruledescriptionfrom“MinimumspacebetweenDGregionand1.8Vtransistorgate”to“MinimumspacebetweenDGregionand1.8Vtransistorchannel(overlapofPolyandAA)alongsource/draindirection.”(DRcommitteedecision)2.1.6DG:changeDG.5ruledescriptionfrom“MinimumenclosureofDGregionbeyond3.3Vtransistorgate”to“Minimumenclosed3.3Vtransistorchannel(overlapofPolyandAA)byDGalongsource/draindirection.”(DRcommitteedecision)3.1.6DG:DG.3:changedescriptionfrom“MinimumspacebetweenDGedgeandAAregion”to“MinimumspacebetweenDGedgeandAAwithdevices”.(DRcommitteedecision)4.1.6DG:AddruleDG.6“OverlapbetweenDGandothervoltageMOSAAisforbidden.”(DRcommitteedecision)5.1.2NW:Modify“Potential”to“net”inNW.2aandNW.2bdescription.(DRcommitteedecision)6.1.2NW:AddRuleNW.4“DummyAAcannotstraddleonaboundaryofNW”(DRlessonlearnextension).7.1.2NW:AddRuleNW.5“ItisnotallowedifN+AA/P+AAstraddleonaboundaryoftheNW”(DRlessonlearnextension).8.1.5AA:AddruleAA.13“MinimumspacebetweenN+AAtoP+AAfornon-butteddiffusioninsamewell(NWorPW)”.(DRcommitteedecision)9.1.5AA:AddRuleAA.14“DummyAAmustnottouchAA,GT,RESAA,RESNW,orRESP1.”(DRcommitteedecision)10.0USERGUIDE:AddNPAAandPPAA,BORDER,RESNW,HRPlayersinPartItable.11.0USERGUIDE:DeleteSNMaskGenerationFormulainPartItable.(DRcommitteedecision)12.0USERGUIDE:AddPartIVGridsizedefinitionin(DRlessonlearnextension).13.1.7Poly:AddruleGT.15“GTmustbeenclosedby(SNorSP)excepttheMOM/MIM,HRPregion.”(DRcommitteedecision)SemiconductorManufacturingInternationalCorporationDoc.No.:TD-LO18-DR-2001Doc.Title:0.18umLogic1P6MSalicide1.8V/3.3VDesignRuleDoc.Rev:8PTechDevRev:2.0PageNo.:4/5959TheinformationcontainedhereinistheexclusivepropertyofSMIC,andshallnotbedistributed,reproduced,ordisclosedinwholeorinpartwithoutpriorwrittenpermissionofSMIC.Accordingto:SMICDocumentControlProcedure;AttachmentNo.:QR-QUSM-02-2001-023;Rev.:12008-06-2714.AddRule1.24BORDER(Chipedge)layerdesignrule.(DRcommitteedecision)15.AddStraddlein1.1DefinitionoftheLayoutLayers(DRlessonlearnextension)16.1.23BONDPADOPENINGRULES:a.Add“PA--”inBONDPADOPENINGRULSEtitleb.deletedescription“Inthissection,weprovideseveralpatternexamplesforpadlayout.Youcanselecttheone(s)whichfitsyourneedmost.”c.deletePA.1/PA.5-PA.10(7pcsrule),