DDR1-DDR2-DDR3-基础知识

DDR1DDR2DDR3BASICKNOWLEDGESUMMARYHulinCao–[e-mail]1/2/3BASICKNOWLEDGEDDRSDRAMBasicKnowledgeDDRStandard&ArchitectureCommands&InitializationDDRSDRAMBasicOperation–Read/Write/Auto-RefreshDQSControlCKEControlBurstOperationNewFeaturesofDDR2SDRAMNewFeaturesofDDR3SDRAMDDR1/2/3BASICKNOWLEDGEDDRSDRAMBasicKnowledgeDDRStandard&ArchitectureCommands&InitializationDDRSDRAMBasicOperation–Read/Write/Auto-RefreshDQSControlCKEControlBurstOperationNewFeaturesofDDR2SDRAMNewFeaturesofDDR3SDRAMDDR–DOUBLEDATARATEStandard:JESD79EIO:SSTL_2,2.5VBanks:4BanksSpeed:DDR200,DDR266,DDR333,DDR400DDRINTERFACEClock:CK,CK#,CKEChipselect:CS#Command:WE#,RAS#,CAS#Address:AnBankaddress:BA0,BA1Data:DQ0~DQn(inout)DataStrobe:DQSn(inout)Datamask:DQMn(1DQMfor8DQ)Power:Vdd,Vss,VddQ,VssQVref:SSTL_2referencevoltageDDRARCHITECTURE2NbitPrefetchDifferentialClockModeRegisterDLLKeysignalsCKEDQSDM2(N)–BITPREFETCHARCHITECTURENmeansthedatawidthofDRAMThekeymethodthatmakesdatarateincreasingDIFFERENTIALCLOCKAddressandCommandsaresampledatthecrossingofCKandCK#OutputdataisreferencedtothecrossingofCKandCK#MODEREGISTERSModeRegisterBurstLength:2/4/8BurstSequence:Sequential/InterleavedCASLatency:1.5/2/2.5/3DLLReset:Normal/ResetSomeothersettingsExtendedModeRegisterDLLEnable/Disable:Enable/DisableDriveStrength:Weak/NormalDLLSynchronizeDQSandDQwithCKinreadflowGuaranteeminimalskewbetweenCKandreaddataReadTimingwithoutDLLDLLINDDRSDRAMReadTimingwithDLLCont’dKEYSIGNALSOFDDRINTERFACECKE–ClockEnableDetermineswhetherCKisvalidornotControlselfrefreshmode&powerdownmodeKEYSIGNALSOFDDRINTERFACEDQS–DataStrobeRead/WritedataissynchronizedtoDQS1bitDQSfor1byteDataCont’dKEYSIGNALSOFDDRINTERFACEDM–DataWriteMaskMaskwritedatawhenDMishigh1bitDMfor1byteDataCont’dDDR1/2/3BASICKNOWLEDGEDDRSDRAMBasicKnowledgeDDRStandard&ArchitectureCommands&InitializationDDRSDRAMBasicOperation–Read/Write/Auto-RefreshDQSControlCKEControlBurstOperationNewFeaturesofDDR2SDRAMNewFeaturesofDDR3SDRAMDDRCOMMANDSDDRCOMMANDSEXECUTABLECONDITIONDDRCOMMANDSTRUTHTABLEDDRINITIALIZATIONApplypower–VDDVDDQVREFVTTandkeepCKElowAfterpowersupply&clockstable,wait200usIssueDESLorNOPcommand(CKEhigh)Prechargeallbanks(PALL)EnableandResetDLL(viaextendedmoderegister)Prechargeallbanks&TwoAutoRefreshSetmoderegistertoprogramoperatingparametersBurstlength,CASlatency,…DDRINITIALIZATIONCont’dDDR1/2/3BASICKNOWLEDGEDDRSDRAMBasicKnowledgeDDRStandard&ArchitectureCommands&InitializationDDRSDRAMBasicOperation–Read/Write/Auto-RefreshDQSControlCKEControlBurstOperationNewFeaturesofDDR2SDRAMNewFeaturesofDDR3SDRAMDDRDATAREADFLOWActiveCommand–Bank&RowtRCDReadCommand–Bank&ColumntCASDataisavailableACTtRASPrechargeCommand–BanktRPThebankbecomesidleTIMINGOFDDRDATAREADFLOWNormalReadTIMINGOFDDRDATAREADFLOWReadwithAuto-PrechargeCont’dBL/2CyclesAfterREADADDRDATAWRITEFLOWActiveCommand–Bank&RowtRCDWriteCommand–Bank&ColumntDQSS(min,max)Writedatacenteralignedatpose/negedgeofDQSACTtRASPrechargeCommand–BanktRPThebankbecomesidleTIMINGOFDDRDATAWRITEFLOWNormalWriteTIMINGOFDDRDATAREADFLOWWritewithAuto-PrechargeCont’dDDRAUTOREFRESHFLOWTwoRefreshModeAutoRefresh–Givemeacommand,thengoaway!SelfRefresh–Shutup!Letmealone!AutoRefreshFlowAllbanksshouldbeIDLE.Ifnot,PrechargeALL!SendREFcommandTherefreshaddresswillbegeneratedbyDRAMinternallytRFCAllbanksbecomeidleTIMINGOFDDRAUTOREFRESHFLOWDDR1/2/3BASICKNOWLEDGEDDRSDRAMBasicKnowledgeDDRStandard&ArchitectureCommands&InitializationDDRSDRAMBasicOperation–Read/Write/Auto-RefreshDQSControlCKEControlBurstOperationNewFeaturesofDDR2SDRAMNewFeaturesofDDR3SDRAMDQSCONTROLDQS–DataStrobeSignalBidirectionalDatavalidindicatedEdge-AlignedforreadCenter-AlignedforwriteDQSCONTROLINREADFLOWDQSissynchronizedwithCK,theDDRcontrollercapturesDQusingDQSastimingreference1.High-Zwhendataisnotinput2.AfterREADcommand,DQSchangestolowabout1cyclepriorreaddataoutput3.DQSstartstogglingatthesamefrequencyasCK4.DQStogglesuntilreadoperationiscompleted,thenDQSgoestoHigh-ZDQSCONTROLINWRITEFLOWDDRcontrollerdriveDQS,whichissynchronizedwithCK,theDDRSDRAMcapturesDQusingDQS1.High-Zwhendataisnotinput2.About½CycleafterWRITEcommand,DQStoggleatsamefrequencyasCK3.DQStogglesuntilwriteoperationiscompleted,½Cycleafterlastwritedata,DQSgoestoHigh-ZRELATIONSHIPBETWEENDQS/DQANDCKINREADFLOWDQS&DQissynchronizedwithCKinReadFlowThepurposeofDLLDQSREADPREAMBLE&POSTAMBLEThedefinitionofDQSPreambleandPostambleDQSREADPREAMBLE&POSTAMBLENoDQSPre/PostambleincontinuousReadBurstTransactionCont’dRELATIONSHIPBETWEENDQSANDDQ/DMDQandDMarecenter-alignedtoDQSDQSWRITEPREAMBLE&POSTAMBLEOccursatfallingedgeofCKafterwritecommandNoDQSPre/PostambleincontinuouswriteburstTransactionCont’dDDR1/2/3BASICKNOWLEDGEDDRSDRAMBasicKnowledgeDDRStandard&ArchitectureCommands&InitializationDDRSDRAMBasicOperation–Read/Write/Auto-RefreshDQSControlCKEControlBurstOperationNewFeaturesofDDR2SDRAMNewFeaturesofDDR3SDRAMCKECONTROLTwomodescontrolledbyCKEPowerDownModeSelfRefreshModeBa