第四章-CMOS组合逻辑电路设计I

1DepartmentofMicroelectronics,PKU，XiaoyanLiu第四章CMOS组合逻辑电路设计I－静态CMOS逻辑门电路第一节互补CMOS逻辑门的结构及性能第二节互补CMOS逻辑门的设计第三节类NMOS电路（有比电路）第四节传输门逻辑电路第五节差分CMOS逻辑电路（有比电路）2DepartmentofMicroelectronics,PKU，XiaoyanLiu第一节静态互补CMOS逻辑电路的结构及性能一、静态CMOS逻辑电路的结构二、静态CMOS逻辑电路的性能3DepartmentofMicroelectronics,PKU，XiaoyanLiuABCVDDYFFF=(BAC,,)PMOSNMOS一、静态CMOS逻辑电路的结构PUNPDNPUN：pullupnet上拉网络PMOSPDN：pulldownnet下拉网络NMOSPUN、PDN为双重网络设计时需保证，无论什么输入，仅有一个网络在稳定状态下导通。4DepartmentofMicroelectronics,PKU，XiaoyanLiu静态CMOS逻辑门特点1）带“非”的逻辑功能input:x1,x2,……,xnoutput:2）逻辑函数F(x1,x2,……,xn)决定于管子的连接关系。NMOS：PMOS：串与并或串或并与),2,1(XnXXFY3）每个输入信号同时接一个NMOS管和一个PMOS管的栅极,n输入逻辑门有2n个管子。4）静态CMOS逻辑门保持了CMOS反相器无比电路的优点。高噪声容限，VOH、VOL分别为VDD和GND5DepartmentofMicroelectronics,PKU，XiaoyanLiuABA+BABA•BNMOS串与并或F1F2F1F2F=F1F2+F=F1F2ABCF=ABCABCF=ABC++6DepartmentofMicroelectronics,PKU，XiaoyanLiuABA•BABABF001011101110AB例：CMOS与非门A•B=A+B[!(A•B)=!A+!Bor!(A&B)=!A|!B]7DepartmentofMicroelectronics,PKU，XiaoyanLiuA+B=A•B[!(A+B)=!A•!Bor!(A|B)=!A&!B]例：CMOS或非门A+BABABF001010100110ABAB8DepartmentofMicroelectronics,PKU，XiaoyanLiuExample:Y=A(B+C)+DY=A(B+C)+DY=A(B+C)+DAAABBBCCCDDDVDD9DepartmentofMicroelectronics,PKU，XiaoyanLiu二、静态CMOS逻辑电路的性能高噪声容限：VOH、VOL分别为VDD和GND，输出电平与器件尺寸无关，无比电路无静态功耗：VDD和GND（VSS）之间没有直流通路在合适的设计时上升、下降时间几乎相同通常空穴迁移率电子迁移率，需要根据n/p将pMOS的尺寸加宽在复杂的组合逻辑门中，性能与输入信号的具体情况有关，即PUN、PDN中的电阻是输入信号的函数，分析难度加大，通常分析最坏情况，可以用等效反相器及开关模型去分析。10DepartmentofMicroelectronics,PKU，XiaoyanLiuAReqARpARpARnCLACLBRnARpBRpARnCintBRpARpARnBRnCLCintNAND2INVNOR2开关模型11DepartmentofMicroelectronics,PKU，XiaoyanLiu例CMOS与非门的分析AABBYYVVDDDDAABBYYABY000001111111ABY001000111100=A.B=A+BMMMN1MN2MMMMN1N2P2P1P2P112DepartmentofMicroelectronics,PKU，XiaoyanLiu直流电压传输特性使用等效反相器方法分析分两种情况：1.两个输入信号同步2.两个输入信号不同步注意：对不同输入状态，等效反相器参数不同。CLBRnARpBRpARnCint13DepartmentofMicroelectronics,PKU，XiaoyanLiu1.两个输入信号同步212121PPPeffNNNNNeffKKKKKKKKVDDVDDVVoutVoutKKKKKKPPPNNNeffeff=2=KKNinVinPP/214DepartmentofMicroelectronics,PKU，XiaoyanLiueffTPDDeffTNVVVitV1)(02/244NPNPNeffPeffKKKKKKeff同步情况下逻辑阈值电平0021)(2TPDDTNVVVitV15DepartmentofMicroelectronics,PKU，XiaoyanLiu2.两个输入信号不同步B固定在VDD，Y随A的关系A固定在VDD，Y随B的关系等效反相器022NPNeffPeffeffKKKK0021)(2TPDDTNVVVitV16DepartmentofMicroelectronics,PKU，XiaoyanLiu二输入与非门的直流电压传输特性ABA•BAB由于衬底偏置效应使M2的阈值大于M1的M2M1AB17DepartmentofMicroelectronics,PKU，XiaoyanLiun输入与非门02nNeffPeffKKeffn个信号输入同步时n个信号输入不完全同步时有（n－1）种情况peffpKnK/NeffNKKn18DepartmentofMicroelectronics,PKU，XiaoyanLiun输入与非门的直流电压传输特性DDnNHMDDNLMVvVVvV)1(100001)1(1)1(1nnnnnPNPNvvK导电因子oCMOS比例因子12effoxWKCL/onpKK归一电平TDDVV噪声容限小于VDD/219DepartmentofMicroelectronics,PKU，XiaoyanLiu瞬态特性近似估算：tPHLtPLH/LDDefffallriseCmVM常数，一般为2－4/efffallrisePUN或PDN的有效比例因子CL门可见的负载电容：•门自加载的，由门中MOSFET尺寸定•连接门的MOSFET的尺寸和数量•门和它驱动的门之间的连线电容RCL20DepartmentofMicroelectronics,PKU，XiaoyanLiuRC电路的延迟若电路中只有R和C并在输入端加阶跃信号0.69RC21DepartmentofMicroelectronics,PKU，XiaoyanLiu•延迟和输入信号相关•Low－high变化–两个输入同时变低•tpLH－0.69Rp/2CL–只有一个输入变低•tpLH－0.69RpCL•High－low变化•两个输入同时变高•tpLH－0.692RnCLCLBRnARpBRpARnCintNAND的延迟估计1tRCoutDDVVe22DepartmentofMicroelectronics,PKU，XiaoyanLiu第二节互补CMOS逻辑门的设计一、电路和版图设计二、组合逻辑门的优化设计三、常见的组合逻辑电路23DepartmentofMicroelectronics,PKU，XiaoyanLiu一、电路和版图设计先设计PDN串与并或利用子单元间的关系得到PUN串或并与F＝A(B+C)+D24DepartmentofMicroelectronics,PKU，XiaoyanLiu+baoutbaoutVDDGNDtubties版图设计NAND的版图25DepartmentofMicroelectronics,PKU，XiaoyanLiu版图设计NOR的版图baoutaboutVDDGNDtubties26DepartmentofMicroelectronics,PKU，XiaoyanLiu组合逻辑门的版图设计方法：1、画图（n图和p图）－2、找欧拉通路－3、求有相同标记的p和n欧拉通路－4、若找不到满足3的通路，则用单独的欧拉通路以达到3的要求。（标记每个点上栅信号标号的次序）目标：将门以最少的端点数目实现连接1、画图把CMOS电路图变换成符号图每个点对应与一条源漏连线每个边对应与一MOSFET，可以用对应的栅信号命名nMOS和pMOS分别对应两个图，n图和p图反映了MOSFET的连接若两条边是相接的，则可共享一个源漏连线并可合并对接27DepartmentofMicroelectronics,PKU，XiaoyanLiu2、找欧拉通路若p图和n图中都存在着包含所有边的一个序列，则该序列称为欧拉（Euler）通路，并且该序列的标记相同，，则这个门可以设计成不间断的扩散行。Eulerpath:apaththroughallnodesinthegraphsuchthateachedgeisvisitedonceandonlyonce.一笔画3、求有相同标记的p和n欧拉通路28DepartmentofMicroelectronics,PKU，XiaoyanLiujVDDXXiGNDABCCABX=!(C•(A+B))BACijABC例PDNPUN29DepartmentofMicroelectronics,PKU，XiaoyanLiuCABX=!(C•(A+B))BACijjVDDXXiGNDABCPUNPDNABC30DepartmentofMicroelectronics,PKU，XiaoyanLiujVDDXXiGNDABCABC相同标记的欧拉通路有些电路找不到相同标记的欧拉通路x=!(a+bc+de)31DepartmentofMicroelectronics,PKU，XiaoyanLiuABCXVDDGNDSingle-Line-of-DiffusionLayoutCABX=!(C•(A+B))BACijStickDiagrams32DepartmentofMicroelectronics,PKU，XiaoyanLiuC•(A+B)XCABABCXVDDGNDVDDGNDSingle-Line-of-DiffusionLayoutDiffusions33DepartmentofMicroelectronics,PKU，XiaoyanLiuVDDXXGNDABCPUNPDNDCABX=!((A+B)•(C+D))BADCDABCD34DepartmentofMicroelectronics,PKU，XiaoyanLiuBADVDDGNDCXCABX=!((A+B)•(C+D))BADCDABCD35DepartmentofMicroelectronics,PKU，XiaoyanLiuGNDxabcdVDDxGNDxabcdVDDx(a)Logicgraphsfor(ab+cd)(b)EulerPaths{abcd}acdxVDDGND(c)stickdiagramforordering{abcd}bx=ab+cd36DepartmentofMicroelectronics,PKU，XiaoyanLiu二、组合逻辑门的优化设计1.减小面积2.提高噪声容限3.提高速度优化设计37DepartmentofMicroelectronics,PKU，XiaoyanLiuCMOS与非门、或非门设计可能的设计方法1.减小面积所有管子取相同尺寸－没有考虑pn，Rp＝2Rn＝2R，N输入NAND和N输入NOR的总面积在2nWL的量级，N输入NANDN输入NORtPLH＝0.69RpCL=2x0.69RCLtPLH=0.69NRpCL=2x0.69NRpCLtPHL＝0.69NRnCL=Nx0.69RCLtPLH＝0.69RnCL=0.69RCL