数字电子技术7890241298

作业反映出来的几个问题1.记对作业题；2.按顺序做题；3.可以不用抄题，但要写清题号；4.答题应尽量体现解题思路和过程；5.按要求交作业，不要跨班；6.作业本写清班号学号。第一章数字逻辑基础1.1.1解：010110101.1.2（2）01110101.3.1（3）254.25254.25D=11111110.01B=376.2O=FE.4H=1001010100.00100101)8421BCD(254.25)D=(11111110.01)B=(376.2)O=(FE.4)H=(1001010100.00100101)8421BCD1.3.2（2）100010010011B=211+27+24+21+20=2195D100010010011BCD=893D1.3.3（2）11.01101B=0011.01101000B=3.68H1.3.4（4）1002.45D=3EA.7333H1.3.5(1)23F.45H=1000111111.01000101B1.3.6(1)103.2H=1x162+3x160+2x16-1=259.125D第二章逻辑门电路2.4.1逻辑0判断VIL=0.8V(1)(2)(3)(4)2.4.2逻辑1判断VIH=2V(1)(2)(3)(4)2.4.3解：(1)LSTTL驱动同类门mAIOL8(max)mAIIL4.0(max)204.08mAmANOLmAIOH4.0(max)mAIIH02.0(max)2002.04.0mAmANOHN=20(2)LSTTL驱动基本TTL门mAIOL8(max)mAIIL6.1(max)56.18mAmANOLmAIOH4.0(max)mAIIH04.0(max)1004.04.0mAmANOHN=52.4.4（1）IOH74LS00=0.4mA2IIH7404+4IIH74Ls00=0.16mAIOL74LS00=8mA2IIL7404+4IIL74Ls00=4.8mA(2)拉电流多余:(0.4-0.16)/0.02=17灌电流多余:(8-4.8)/0.4=8N=min(8,17)=82.4.5EDBCABEDBCABL__________________________2.4.6RP计算(1)拉电流时VOH740100747401)OLLSILOLPCCVIIRV（KmAVVIVVRLSIHOHCCP13002.04.250074740174010074OHLSIHPCCVIRV740174LS00(2)灌电流时KmAmAVVIIVVRLSILOLOLCCP29.04.0164.050074740174012.9.1驱动:负载:拉电流:灌电流:扇出:2.9.2VOHVIHVOLVILIOHIIHIOLIIL第三章组合逻辑电路分析与设计3.1.3代数法化简（a）ABABABCABCAB)(CABCCBCACBABCBCBACBBCA))(()(_______（c）0_____________________________________AABABABAAB（e）3.1.2证明（C）ECDAECDCDAEDCCDAAEDCCDACBAA_____)(BABABABAABBAAB))(()()(__________________________________（i）（g）BACBACBA))((DBCBABDACABDCADACBDBCBABDABCDCBABDABCCDCBABDABCCBABCDDBCABDDABC)()()()(（k）（m）0)()()()(________________________________________________________________________________________________________________________________________________________________________________________ACBAABACBAABABCBABABAABCBA3.1.4变换与或式(b)DBCACDCDBDBCADACDBADCDADCDCBADADCDCBA))(())(())((__________________________________________________________________3.1.6变换2输入与非DCBADBCADBCALCABACABACABACABAL3.1.7与非(a)_______________________ACABACABACABL3.1.8或非(a)3.2.1展开最小项(a)imBCAACCBBACBACBAL)())(()(3.2.2(a)CCABCCABCACCABCBBCACCABCBBCAAC____________________________________________________(c)BCDABDCBCBADABBCDABDDCBCBAABDCABDDCBCBABADCABDCDBBA)()()()(__________________000111100011011111111110(e))15,14,13,12,10,9,8,7,6,5,4,3(),,,(mDCBAL)15,11,7,5,3,2()13,9,6,4,1,0(),,,(dmDCBAL(g)CDBADACDCADBCBABDA3.2.3略3.3.3一位数值比较器BAABBABALLLBABALBABAL212313.3.5:输入端奇数个1，L=1，否则为0，即为奇偶校验器DCBAL3.4.2)14,12,10,9,8,4,2(mL00011110001011111110111DCBCBADCBDADCBCBADCBDA(a)与或非DCBCBADCBDADCBCBADCBDADCBCBADCBDADCBCBADCBDADCBCBADCBDADCBCBADCBDADCBCBADCBDA(b)与非(c)或非3.4.4CLi0A’I1AIiACiiiCAACL第四章组合逻辑器件4.1.1输入输出I3I2I1I0D7D6D5D4D3D2D1D0100010110011010011010101001001111010000111001101其它全0或全14.1.4输出端增加一级非门4.2.3764076407640YYYYYYYYmmmmABCCABCBACBAF4.2.432个地址译码电路设计分析：32个地址译码需要4片74138，5位译码输入，高2位用片选实现，低3位用原输入并联。ED74138(1)0074138(2)0174138(3)1074138(4)11DE00H-07H80H-0FH10H-17H18H-1FHABC4.2.5(1)逻辑门设计DCBACDBAYDCBADCBAY90(2)74138实现D=0选中低位片1；D=1选中高位片2120100ABCD01234567894.2.97位数字译码显示电路整数部分小数部分4.3.44选1数据选择器ES3S2S1S0Y’10001I010010I110100I211000I30XXXX高阻][30123201231012300123ISSSSISSSSISSSSISSSSEY最后一级与门使用三态与门4.3.574151输出波形4.3.6(2)74151输出波形7421mmmmABCBCACBACABY00100111001100111100111111BAABABBABABABABABABABABABAFBA4.4.1三个3输入与门和一个或门实现”AB“4.4.3设计8位相同数值比较器，数值相等输出L=1，否则为077665544332211007766554433221100BABABABABABABABABABABABABABABABAiiBALL4.5.1用半加器和或门构成一个全加器1iiiiCBAS1iiiiiiCBABAC全加器：半加器：ABCBAS1-ii1SCCCiiCSS4.5.6(1)半减器BABASBAC(2)全减器11111iiiiiCBAABCCBACBACBAS11111iiiiiiCABBABAABCBCACBACBAC