基于误差修正算法的并行交替采样ADC的应用

基于误差修正算法的并行交替采样ADC的应用并行交替采样ADC原理并行交替采样ADC（Time-interleavedADC,TI-ADC)结构能够将多片相对低采样率的ADC芯片组合起来构成高采样率系统。InputAnalogSignalADCADCADC01M010011TDealyClockfs/MMMMTI-ADC的缺陷由于制造工艺的原因，通道间失配误差会降低整个TI-ADC系统的SNR和SFDR.三种失配误差:偏置误差（OffsetError）增益误差（GainError）采样间隔误差（Timing-skewError）增益误差（GainMismatch)增益失配的示意图增益失配的时域和频域分析时域分析频域分析基本误差信号周期等于单个ADC采样周期（fs/M）误差信号的幅度被输入正弦信号的幅度所调制最大误差发生在输入正弦波的峰值处误差信号的包络线频率等于输入正弦波频率频域中的噪声峰：fnoise=fin+kxfs/M噪声频率与输入信号频率相关噪声频率与采样频率相关k=i/M采样间隔误差（PhaseMismatch)时钟相位失配的示意图时钟相位失配的时域和频域分析时域分析频域分析基本误差信号周期等于单个ADC采样周期（fs/M）误差信号的幅度被输入正弦信号的导数所调制最大误差发生在输入正弦波的过零处误差信号的包络线频率等于输入正弦波频率，但相相位与增益误差信号相差90度频域中的噪声峰：fnoise=fin+kxfs/M噪声频率与输入信号频率相关噪声频率与采样频率相关k=i/M偏置误差（OffsetMismatch)偏置失配的示意图偏置失配的时域和频域分析时域分析频域分析误差与输入信号在时域和频域均无关误差信号周期等于单个ADC采样周期频域中的噪声峰：fnoise=kxfs/m噪声频率与采样频率相关k=i/M三种误差的总效应SignalcomponentTimeandgainerrordistortionOffseterrordistortion1,...,1,0MisMiTotalMismatcherror:增益和时间相位误差：偏置误差：1,...,1,MisMi数字后处理系统框图数字后处理算法研究误差估计算法误差修正算法ADC0ADC1ADCM-1CorrectIon△tMUXTimeerrorestimationalgorithmZ1(△t)ZM-1(△t)Z0(△t)Z(△t)Delay,Ts混合滤波器组系统分析——TI-ADCTI-ADC：,0,,1smsjmTrTmHjemMH0(s)H1(s)HM-1(s)F0(z)F1(z)FM-1(z)Synthesisfilterbank(Descrete-Time)x0(t)x1(t)xM-1(t)↑M↑M↑MAnalysisfilterbank(Continuous-Time)x(t)ADCADCADCx0[k]x1[k]xM-1[k]v0[n]v1[n]vM-1[n]y0[n]y1[n]yM-1[n]TI-ADC重构滤波器（1）假设x(t)是1stNyquist内的带限信号，则y(n)的Fouriertransformation可以写成：其中：1112,MjjppMssspYeTeXjjTTMT1012MjjpmmmsspTeFeHjjMTMT012-ππ-π/3π/3-1-2-4π/3-2π4π/32π0-π/Ts(a)(b)π/TsX(jΩ)Ωω-33M=3X(jω/Ts-j2πp/(MTs))TI-ADC重构滤波器（2）重构滤波器：其中与α(m+1)k是矩阵A-1(d)的元素111,010,1;.mjddjkdmmkFkMeemkMId011,,2IM,0,1,,1.mmdmrmMTI-ADC重构滤波器（3）重构滤波器的冲激响应1010,sinsinMiimMmmiiimnddMMfnnddddM-8-6-4-2024681012-0.6-0.4-0.200.20.40.60.811.2Time[Ts]Amplitude[V]TI-ADC重构滤波器（4）重构滤波器组的多相实现结构：频率相关的修正方法TI-ADC硬件设计模拟输入信号1:M拆分与驱动低失真一致性好多相时钟产生低抖动精确相移14bit320MspsTIADC（1）14bit80MSPSADC14bit80MSPSADC14bit80MSPSADC14bit80MSPSADCPost-ProcessingCycloneIIFPGAEP2C3532768×36BitFIFOPS1:432768×36BitFIFO80MHzMulti-PhaseClockGeneratorInterfaceCycloneFPGAEP1C6VMEBusThereareFourADCsoperateinparallelImplementedthePost-Processing4ADCsAD6645ImplementedthePost-Processing14bit4GspsTIADC14bit320MspsTIADC（2）模拟前端：功分器+变压器多相时钟产生：分立锁相环结构FPGA内实时修正失配误差PLLLoopFilterClockRefVCSOClockDistribuationAD9510Out0Out1Out2Out3Clk2x0[k]x1[k]x3[k]Δoff0Δoff1Δoff31+Δg01+Δg21+Δg30[]yk1[]yk1[]Myk[]yn0,00,33,03,3FzFzFzFz14bit320MspsTIADC（3）Fin=59.0MHzOffsetError:(LSB)18.99.019.114.0GainError:(%)0-2.01-1.57-0.80TimeError:(ps)0-2.615.137.60246810121416x107-120-100-80-60-40-20020Frequency(Hz)Power(dB)SignalcomponentOffsetErrorDistortionTime&GainErrorDistortion0246810121416x107-120-100-80-60-40-20020Frequency(Hz)Power(dB)SignalcomponentOffsetErrorDistortionTime&GainErrorDistortion修正前:SINAD=40.1dBSFDR=41.0dB修正后:SINAD=66.4dBSFDR=92.1dB8bit4GspsTIADC（1）8bit4GspsTIADCAT84AD001BADC数据接收和存储8bit4GspsTIADC（2）模拟前端：功分器+变压器多相时钟产生：集成锁相环+延迟线高速LVDS信号接收8bit4GspsTIADC（3）Fin=803.0MHzOffsetError:(LSB)0-3.78-10.66-3.38GainError:(%)0-2.65-0.48-1.69TimeError:(ps)0-39.63-22.91-81.22修正前:SINAD=17.3dBSFDR=19.4dB修正后:SINAD=35.4dBSFDR=50.8dB00.20.40.60.811.21.41.61.82x109-120-100-80-60-40-20020Frequency(Hz)Power(dB)SignalcomponentOffsetErrorDistortionTime&GainErrorDistortion00.20.40.60.811.21.41.61.82x109-120-100-80-60-40-20020Frequency(Hz)Power(dB)SignalcomponentOffsetErrorDistortionTime&GainErrorDistortion8bit500MspsTIADC（1）AD9480AD9480ClockgeneratoranddistributorDDRSDRAMPCIinterfaceDDRInterfaceVGAcontrollogicPCIbusSignalinputVariableGainAmplifierFPGA8bit500MspsTIADCAD9480ADC数据接收和存储8bit500MspsTIADC（2）模拟前端：可变增益放大器多相时钟产生：集成锁相环DDRSDRAM大容量数据缓存8bit4GspsTIADC（3）Fin=50.0MHzOffsetError:(LSB)0-4.1GainError:(%)01.006TimeError:(ps)047.3修正前:SINAD=35.5dBSFDR=35.2dB修正后:SINAD=44.6dBSFDR=62.8dB050100150200250-90-80-70-60-50-40-30-20-10010Thefigureofthefrequencedomain(multipleFFT)[-1.19dB]AnalogInputFrequency(MHz)Amplitude(dB)23456789050100150200250-90-80-70-60-50-40-30-20-10010Thefigureofthefrequencedomain(multipleFFT)[-1.25dB]AnalogInputFrequency(MHz)Amplitude(dB)23456789Thanks!